A device for decoding a generalized concatenated code (GCC) codeword includes: a buffer; and at least one processor configured to: obtain the GCC codeword, calculate a plurality of inner syndromes based on a plurality of frames; calculate a plurality of sets of delta syndromes based on the frames; determine a plurality of outer syndromes based on the sets of delta syndromes; store the inner syndromes and the outer syndromes in a buffer; perform inner decoding on the frames based on the inner syndromes stored in the buffer; update at least one outer syndrome stored in the buffer based on a result of the inner decoding; perform outer decoding on the frames based on the updated at least one outer syndrome; and obtain decoded information bits corresponding to the GCC codeword based on a result of the inner decoding and the result of the outer decoding.

A soft input decoding method and a decoder for generalized concatenated (GC) codes. The GC codes are constructed from inner nested block codes, such as binary Bose-Chaudhuri-Hocquenghem, BCH, codes and outer codes, such as Reed-Solomon, RS, codes. In order to enable soft input decoding for the inner block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In one aspect, the present invention applies instead a representation of the block codes based on the trellises of supercodes in order to reduce the memory requirements for the representation of the inner codes. This enables an efficient hardware implementation. In another aspect, there is provided a soft input decoding method and device employing a sequential stack decoding algorithm in combination with list-of-two decoding which is particularly well suited for applications that require very low residual error rates.

The disclosed systems, structures, and methods are directed to encoding and decoding information for transmission across a communication channel. The method includes dividing the information between m parallel polar codes such that each of the m parallel polar codes includes a plurality of information bits, and splitting the information bits in each of the m parallel polar codes into a private part and a public part. The public part includes an information section and a repetition section, wherein the information bits of the public part are arranged in the information section. Bits in the information section of the public part of each of the m parallel polar codes are repeated in the repetition section of the public part of at least a second one of the m parallel polar codes.

A memory system that detects and corrects bit errors performs a first decoding procedure regarding a serial unit of the encoded data to produce a decoded serial unit. The memory system further determines the first decoding procedure regarding the serial unit was not successful and performs the first decoding procedure regarding a plurality of additional serial units of the encoded data to produce a plurality of additional decoded serial units. The serial unit and the plurality of additional serial units constitute a predefined grouping of the encoded data. The memory system also performs a second decoding procedure regarding a plurality of derivative units to produce a plurality of decoded derivative units. Each successive bit in each of the plurality of derivative units is correlated to a corresponding sequential position in the decoded serial unit and each of the decoded additional serial units.

Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

A Polar code decoding method and apparatus, a storage medium, and a terminal are provided. The method includes: dividing a Polar code having a length of N into S groups of Polar codes, each group of the S groups of Polar codes being data extracted from the Polar code having the length of N according to a preset rule, and S being an integer power of 2; and performing joint decoding on calculation results of the S groups of Polar codes after performing a logarithm likelihood ratio (LLR) calculation on each group of the S groups of Polar codes.

A decoding method and device for Turbo product codes, a decoding device, a decoder and a computer storage medium are provided. The method includes: a received codeword of a Turbo product code is acquired, and iterative decoding is performed on the received codeword for a set first iterative decoding times (S101); a decoding result of iterative decoding performed for the first iteration times is judged according to a first decoding rule to obtain a decoding identifier representing the decoding result (S102); and error correction processing is performed on the Turbo product code on which iterative decoding is performed for the first iteration times according to the decoding identifier (S103).

The present disclosure relates to a pre-5.sup.th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4.sup.th-generation (4G) communication system such as a long term evolution (LTE). A method for transmitting a signal in a signal transmitting apparatus in a communication system supporting a bit-interleaved coded modulation with iterative decoding (BICM-ID) scheme is provided. The method includes performing an outer encoding operation; performing an interleaving operation on the outer code corresponding to an interleaving scheme which is based on a preset generation matrix to generate an interleaved signal; performing an inner encoding operation; performing a modulating operation; and transmitting the modulated signal, wherein the generation matrix is generated by applying at least one of a preset column permutation rule and a preset row permutation rule to a generation matrix for a quasi-cyclic (QC) interleaver.

A hard-decision (HD) forward error correcting (FEC) coded signal is decoded by a decoder to produce decoded bits using marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal. The marked reliable and unreliable bits are computed by calculation and marking blocks based on an absolute value of log-likelihood ratios of the HD-FEC coded signal. The HD-FEC coded signal may be, for example, a staircase code coded signal or a product code coded signal.

In an optical disc apparatus that records and reproduces data onto and from an optical disc in units of predetermined block, an information divider divides the data so as to reduce an amount of the data included in each of blocks when a recording state of the optical disc does not satisfy a predetermined criterion, and reproduces recording data in units of the block by adding sub-information including a value indicating the amount of the data included in each of the blocks. An error-correction encoder circuit encodes the recording data in a first error-correction code format, and a recorder converts encoded recording data into a recording signal, and records the recording signal onto the optical disc. A quality evaluator circuit produces an evaluation value indicating a recording quality based on a result of reproducing the recording signal recorded on the optical disc.