Example systems, read channel circuits, data storage devices, and methods to use inter-symbol interference message passing (ISI-MP) data in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, configured to determine both the first most likely and second most likely sets of symbols and output inter-symbol interference data based on the adjacent symbols and corresponding ISI in each set of symbols. The inter-symbol interference data may be used by an ISI-MP circuit configured to model ISI-MP and provide feedback to an iterative decoder during local iterations.

Control information for configuring an audiovisual device to present multimedia content according to a first service type may be generated. A method may include generating first control information for configuring an audiovisual device to decode a multimedia stream, generating first data that indicates a structure of the first control information, and transmitting the first data and the first control information. The first control information may be generated according to a first protocol version. Second data and second control information may be similarly generated and transmitted according to a second protocol version. Disclosed techniques may facilitate receiving devices to determine whether they support received wireless transmissions and decode the transmissions based on the control information.

An operating method of a controller includes: a first step of generating an internal codeword including an ECC unit data and an internal parity code by performing ECC decoding operation to an input data; a second step of updating an external parity code based on the ECC unit data, which is included in the internal codeword currently generated, and the ECC unit data, which is included in the internal codeword previously generated; and a third step of storing in a semiconductor memory device one or more internal codewords and the updated external parity code, which are generated through repetition of the first and second steps, by a unit of predetermined storage size.

A memory controller performs an error recovery operation. The controller performs a read operation on a select block using a select read level; decodes data associated with the read operation to generate a syndrome value; determines whether to stop, before a maximum number of iterations, the read operation and the decoding at the select read level, using the syndrome value; when it is determined to stop the read operation and the decoding at the select read level, selects a next read level in a sequence of read levels; and uses the next read level for a subsequent read operation.

In various embodiments, a method of using a memory device is provided. The method may include storing data units, check units of a first code and check units of a second code in memory cells of the memory device, wherein the data units and the check units of the first code form code words of the first code, and wherein the data units and the check units of the second code form code words of the second code, applying the second code for error correction in at least a portion of the data units and/or in at least a portion of the check units of the first code, after the correcting the errors, retaining at least a retaining portion of the data units and of the check units of the first code and deleting at least a deleting portion of the check units of the second code, thereby freeing the memory cells that are occupied by the deleting portion of the check units of the second code, and during a subsequent using of the memory device, storing data in at least a reuse portion of the freed-up memory cells.

An operating method of a controller includes generating error reliability of data based on reliability information of one or more error-corrected bits of the data, wherein the data is read out from a semiconductor memory device and a hard decision ECC decoding to the data through a BCH code is determined as successful; and determining miscorrection of the data based on the error reliability.

Low-density parity-check (LDPC) coding based on memory cell voltage distribution (CVD) in data storage devices. In one embodiment, a memory controller includes a memory interface configured to interface with a non-volatile memory; and a controller. The controller is configured to receive a plurality of data pages to be stored in the non-volatile memory, and transform the plurality of data pages into a plurality of transformed data pages. The controller is further configured to determine a plurality of parity bits based on the plurality of transformed data pages, and store the plurality of data pages and the plurality of parity bits in the non-volatile memory.

A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

A device includes a memory and a controller coupled to the memory. The controller is configured to maintain a first address translation table associated with the memory and a second address translation table associated with the memory. The controller is further configured to receive a command to erase the memory. The controller is further configured to switch an indicator of an active address translation table from the first address translation table to the second address translation table in response to receiving the command.

A data processing device includes decoder circuits, a checker circuit, and a control circuit. The decoder circuits set groups of first sampling points and groups of second sampling points according to an initial transition edge of a first signal, and perform a parallel decoding on the first signal according to the groups of first sampling points and the groups of second sampling points, in order to generate a second signal and a third signal. The checker circuit checks the second signal and the third signal, in order to generate a check result. The control circuit selects at least one of the decoder circuits according to the check result for receiving subsequent data.