In one embodiment, an apparatus for decoding is disclosed. The apparatus includes a memory and at least one processor coupled to the memory. The at least one processor is configured to obtain one or more parameters corresponding to a system, determine a plurality of settings corresponding to an adaptive soft decoding procedure for decoding a product code, wherein the plurality of settings are determined based on the one or more parameters using a trellis, and determine a decoded codeword by performing the adaptive soft decoding procedure on the received codeword, wherein the adaptive soft decoder utilizes the determined plurality of settings.

A data storage device may include a memory and a controller that includes an error correction coding (ECC) decoder configured to operate in a plurality of decoding modes. The controller also includes a bit error rate estimator configured to determine, based on data received from the memory, bit error rate estimates for ECC codewords from the memory. The controller also includes a data path management unit configured to reorder the codewords based on the bit error rate estimates and to provide the reordered codewords to the ECC decoder.

In an illustrative example, an apparatus includes a controller and a memory that is configured to store a codeword of a convolutional low-density parity-check (CLDPC) code. The codeword has a first size and includes multiple portions that are independently decodable and that have a second size. The controller includes a CLDPC encoder configured to encode the codeword and a CLDPC decoder configured to decode the codeword or a portion of the codeword.

A method is proposed for decoding read bits including information bits from memory cells of a solid state drive. The method comprises determining a reliability indication indicative of a reliability of the read bits, and iterating the following sequence of steps: soft decoding the read bits based on said reliability indication in order to obtain said information bits, determining at least one among a time indication indicative of a time elapsed since a last writing of the memory cells and a temperature indication indicative of a temperature of the memory cells, and applying at least one among said time indication and said temperature indication to said reliability indication.

A corresponding solid state drive is also proposed.

A method is proposed for decoding read bits including information bits from memory cells of a solid state drive. The method comprises providing an indication of reliability of the read bits, and, based on said indication of reliability, iteratively soft decoding the read bits in order to obtain said information bits. Said soft decoding comprises, at each iteration of the soft decoding, if the current number of iterations has reached a predetermined number of iterations indicative of an admitted latency of the solid state drive, and if no information bits having an error rate below a predetermined error rate have been obtained, providing a further indication of reliability of the read bits, and iteratively soft decoding the read bits based on said further indication of reliability.

A corresponding solid state drive is also proposed.

A method is proposed for decoding bits stored in memory cells of a solid state drive. Each memory cell comprises a floating gate transistor adapted to store a bit pattern, among a plurality of possible bit patterns, when programmed at a threshold voltage associated with that bit pattern, each threshold voltage being variable over the memory cells thereby defining, for each bit pattern, a corresponding threshold voltage distribution. The bit pattern of each memory cell comprises first and second bits, and the solid state drive is suitable for reading the bit patterns based on fixed reference voltages, each one designed to discern between two respective adjacent threshold voltage distributions, and on additional reference voltages different from the fixed reference voltages. The solid state drive is capable of soft decoding the read bit patterns based on soft information. The method comprises:

reading the first and second bits of the memory cells based on the fixed reference voltages, to obtain read first bits and read second bits, and

soft decoding the read first bits, wherein the soft information exploited for soft decoding the read first bits are based on the read second bits.

A corresponding solid state drive is also proposed.

In an illustrative example, a method includes sensing at least a portion of a representation of a convolutional low-density parity-check (CLDPC) codeword stored at a memory of a data storage device. The method further includes receiving the portion of the representation of the CLDPC codeword at a controller of the data storage device. The method further includes performing one or more management operations associated with the memory based on an estimated number of errors of the portion of the representation of the CLDPC codeword.

A decoding method includes: receiving a plurality of subcarrier signals each including encoded data; acquiring a predetermined amount of data from each of the plurality of subcarrier signals; correcting errors in the plurality of subcarrier signals by performing decoding arithmetic processing on the respective predetermined amounts of data acquired from the plurality of subcarrier signals in a time-division manner; and causing the decoding arithmetic processing to be consecutively performed on each of the predetermined amounts of data a predetermined number of times.

An encoder and decoder using LDPC-CC which avoid lowering the transmission efficiency of information while not deteriorating error correction performance, even at termination; and an encoding method of the same. A termination sequence length determining unit determines the sequence length of a termination sequence transmitted added to the end of an information sequence, according to the information length (information size) and encoding rate of the information sequence. A parity calculation unit carries out LDPC-CC coding on the information sequence and the known-information sequence necessary for generating a termination sequence of the determined termination sequence length, and calculates a parity sequence.

A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory has data encoded with an error correction code stored therein. The memory controller reads data from the nonvolatile memory, calculates likelihood information from the read data and an LLR table for calculating the likelihood information, determines a parameter for a decoding process of the read data based on the likelihood information, executes the decoding process based on the determined parameter, and outputs a decoding result obtained by the decoding process.