Method for decoding signal includes receiving signal, where signal includes at least one symbol; decoding signal in stages, where each at least one symbol of signal is decoded into at least one bit per stage, wherein Log-Likelihood Ratio (LLR) for each at least one bit at each stage is determined, and identified in vector L.sub.APP; performing Cyclic Redundancy Check (CRC) on L.sub.APP, and stopping if L.sub.APP passes CRC; otherwise, determining magnitudes of LLRs in L.sub.APP; identifying K LLRs in L.sub.APP with smallest magnitudes and indexing K LLRs as r={r(1), r(2), . . . , r(K)}; setting L.sub.max to maximum magnitude of LLRs in L.sub.APP or maximum possible LLR quantization value; setting v=1; generating {tilde over (L)}.sub.A(r(k))=L.sub.A(r(k))L.sub.maxv.sub.ksign[L.sub.APP(r(k))], for k=1, 2, . . . , K; decoding with {tilde over (L)}.sub.A to identify {tilde over (L)}.sub.APP, wherein {tilde over (L)}.sub.APP is LLR vector; and performing CRC on {tilde over (L)}.sub.APP, and stopping if {tilde over (L)}.sub.APP passes CRC or v=2.sup.K-1; otherwise, incrementing v and returning to generating {tilde over (L)}.sub.A(r(k)).

A set of bits of a data block that is associated with an unsuccessful first decoding operation may be identified. A second decoding operation to simulate switching at least one bit of the set of bits may be performed. At least one bit of the set of bits switched during the performance of the second decoding operation may be determined to correspond to an error. The error from the at least one bit of the set of bits may be corrected by changing a value of the at least one bit.

A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory has data encoded with an error correction code stored therein. The memory controller reads data from the nonvolatile memory, calculates likelihood information from the read data and an LLR table for calculating the likelihood information, determines a parameter for a decoding process of the read data based on the likelihood information, executes the decoding process based on the determined parameter, and outputs a decoding result obtained by the decoding process.

A flash memory controller is configured to decode a codeword. During the decoding process, the flash memory can check the decoding status of each codeword segment in the codeword and skip the decoding of a codeword segment whose decoding status is passed, thereby saving time decoding and also improving decoding efficiency. Even though only a part of the codeword segments in the codeword have been successfully decoded in the decoding process at the previous time, the flash memory controller can replace the part of the codeword segments in the codeword with the correct results obtained previously, and then decoding the re-formed codeword again. Accordingly, the decoding accuracy can be increased and the burden on the subsequent decoding process or data recovery can be reduced.

Techniques are described herein to terminate a list decoding operation before its completion based on performing one or more error check processes. A transmitted codeword encoded using a polar code may include one or more error check vectors interspersed with one or more information vectors. Upon receiving the codeword, a decoder may perform a list decoding operation on the received codeword. Upon decoding one of the error check vectors, the decoder may determine whether at least one candidate path used in the successive cancellation list decoding operation passes an error check process based on the error check vector. If no candidate paths satisfy the error check process, the decoder may terminate the list decoding operation. In some examples, the decoder may recheck whether candidate paths satisfy the error check operation at intermediate positions between error check vectors. Such rechecking may occur while decoding information vectors.

This application discloses a transmission method, a transmission apparatus, and a communications device. The transmission method includes: performing polar encoding on a bit sequence, to obtain an encoded sequence, where the bit sequence includes control information and a cyclic redundancy check CRC sequence; fragmenting the encoded sequence, to obtain n encoded subsequences, where n is an integer, and n>0; and scrambling the n encoded subsequences by using n scrambling sequences respectively, to obtain n scrambled sequences. In the transmission method, the n scrambling sequences are newly defined based on encoding and decoding features of a polar code, and the n scrambling sequences additionally carry log.sub.2n-bit information. According to the foregoing encoding method, signaling overheads are reduced.

In an aspect of the disclosure, a method, a computer-readable medium, and wireless equipment are provided. The wireless equipment obtains an integer E and an integer N. E encoded bits are to be selected for transmission from N encoded bits output from an encoder. The wireless equipment determines F inputs from N inputs of the encoder based on E and N. The F inputs do not include S inputs that correspond to S outputs of the encoder generating encoded bits not to be transmitted. The wireless equipment sets the F inputs to a predetermined value.

Enhanced error correction for data stored in storage devices are presented herein. An error correction circuit decodes an encoded data segment retrieved from a storage media. This decode uses a selected error correction scheme having an error correction limit. The error correction circuit tracks a number of bit corrections made to the encoded data segment during decode. A detection circuit sends a redundant version of the encoded data segment to the error correction circuit in response to the number of bit corrections satisfying a threshold limit set below the error correction limit to mitigate undetected errors in decoding the encoded data segment. An output circuit can transfer resultant data decoded by the error correction circuit to other systems, such as a host device.

A method of correcting one or more bit errors in a memory device includes retrieving a codeword from a memory device. The codeword includes a data and an error correcting code. The method further includes determining whether the one or more bit errors are present in the retrieved codeword and correcting the retrieved codeword for the one bit error in response to determining one bit error is present in the retrieved codeword. The method also includes flipping a bit of the retrieved codeword in response to determining a plurality of bit errors is present in the retrieved codeword and correcting the retrieved codeword for the plurality of bit errors based on the bit-flipped codeword.

Methods and systems for analyzing data are disclosed. An example method can comprise receiving a first data signal, decoding the first data signal, determining a second data signal based on the decoded first data signal, and determining a modulation error ratio based on a difference between the first data signal and the second data signal.