Iterative signal processing. At communication hardware, a signal is received from a transmission medium. The signal has characteristics that obscure data or a signal of interest in the signal. The signal is processed at a first signal processor, which is an iterative processor that performs signal processing in cycles whereby successive cycles: improve the performance of processing of the processor itself over previous cycles, or improve the output from the processor. The signal is processed at one or more second signal processors. Extrinsic data, with respect to the first signal processor is produced as a result. The extrinsic data is provided to the first signal processor and used to counter the effects of the data or signal of interest being obscured in the signal, while the first signal processor is intracycle of a first processing cycle.

In certain aspects, a controller for controlling a memory device includes a memory and a processor. The memory is configured to store instructions. The processor is coupled to the memory and configured to execute the instructions to perform a process including receiving data describing a read failure of a set of error handling mechanisms, where the read failure indicates that the set of error handling mechanisms handles a read error on a block of the memory device and fails to read data stored in the block; and responsive to the read failure of the set of error handling mechanisms, performing a memory test on the block to determine whether the block malfunctions.

The present application concerns an iterative bit-flipping decoding method using symbol or bit reliabilities, which is a variation of GRAND decoding and is denoted by ordered reliability bits GRAND (ORBGRAND). It comprises receiving a plurality of demodulated symbols from a noisy transmission channel; and receiving for the plurality of demodulated symbols, information indicating a ranked order of reliability of at least the most unreliable information contained within the plurality of demodulated symbols. A sequence of putative noise patterns from a most likely pattern of noise affecting the plurality of symbols through one or more successively less likely noise patterns is provided. Responsive to the information contained within the plurality of symbols not corresponding with an element of a code-book comprising a set of valid codewords, a first in the sequence of putative noise patterns is used to invert the most unreliable information of the information contained within the plurality of symbols to obtain a potential codeword, and responsive to the potential codeword not corresponding with an element of the code-book, repeatedly: a next likely noise pattern from the sequence of putative noise patterns is applied to invert a noise effect on the received plurality of demodulated symbols to provide a potential codeword, each successive noise pattern indicating an inversion of information for one or more demodulated symbols for a next more reliable combination of information contained within the plurality of symbols, until the potential codeword corresponds with an element of the code-book.

This application discloses decoding methods, apparatuses, and computer-readable storage media, which may be applied to a plurality of scenarios such as a metropolitan area network, a backbone network, and data center interconnection. An example method includes: obtaining syndromes corresponding to a plurality of codewords; grouping the syndromes into groups; and sorting priorities of each group of syndromes; and selecting, based on a priority sorting result of each group of syndromes, a syndrome for decoding.

One example of erasure-assisted error correction code (ECC) decoding can include reading a codeword with a first trim level, reading the codeword with a second trim level, and reading the codeword with a third trim level. A first result from reading the codeword with the first trim level, a second result from reading the codeword with the second trim level, and a third result from reading the codeword with the third trim level can be accumulated. An erasure of a detected unit sequence can be computed. The detected unit sequence can be modified by changing a unit in a position of the detected unit sequence corresponding to a position of the erasure. The modified detected unit sequence can be ECC decoded.

A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, each data block having a number of data bits. The decoding apparatus is configured to decode in parallel two or more codewords, which share a common data block, to determine error information associated with each codeword. For each error, the error information identifies a data block having the and associated error bit patterns. The decoding apparatus is configured to update the two or more codewords based on the identified data blocks having errors and the associated error bit patterns.

Example systems, read channel circuits, data storage devices, and methods to provide signal correction based on soft information in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, and a signal correction circuit. The soft output detector passes detected data bits and corresponding soft information to the signal correction circuit. The signal correction circuit uses the soft information to determine a signal correction value, which is combined with input signal to return a corrected signal to the soft output detector for a next iteration. In some configurations, the signal correction value may compensate for DC offset, AC coupling poles, and/or signal asymmetries to reduce baseline wander in the read channel.

The present disclosure relates to a communication method and system for converging a 5.sup.th-Generation (5G) communication system for supporting higher data rates beyond a 4.sup.th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. Further, the present disclosure relates to decoding of a turbo code in a communication system including long term evolution (LTE), and to efficiently implement a method, procedure, and device for receiving and decoding a signal transmitted in a mobile communication system.

Examples relate to a decoding apparatus, a decoding device, a decoding method, a decoding computer program, and a communication device, a memory device and a storage device comprising such a decoding apparatus or decoding method. A decoding apparatus for performing iterative decoding on a codeword comprises processing circuitry comprising a plurality of processing units, and control circuitry configured to control the iterative decoding of the codeword. The iterative decoding is based on a parity-check matrix. The matrix is sub-divided into two or more partitions. The control circuitry is configured to operate in a first mode of operation to process a codeword having a first length, and to operate in a second mode of operation to process a codeword having a second length. The control circuitry is configured to multiplex the utilization of the plurality of processing units across the two or more partitions of the matrix at least in the second mode of operation.

A method and apparatus for decoding quasi-cyclic LDPC codes using a vertical layered iterative message passing algorithm. The algorithm of the method improves the efficiency of the check node update by using one or more additional magnitudes, predicted with predictive magnitude maps, for the computation of messages and update of the check node states. The method allows reducing the computational complexity, as well as the storage requirements, of the processing units in the check node update. Several embodiments for the apparatus are presented, using one or more predictive magnitude maps, targeting significant savings in resource usage and power consumption, while minimizing the impact on the error correction performance loss.