An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.

A data processing method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first write data; performing a first stage encoding operation of a low-density parity-check (LDPC) code on the first write data and generating first transition data; performing a second stage encoding operation of the LDPC code on the first transition data and generating a first error correcting code (ECC); receiving second write data; and performing the first stage encoding operation of the LDPC code on the second write data during a time period of performing the second stage encoding operation of the LDPC code on the first transition data. Accordingly, the data processing efficiency corresponding to the LDPC code can be improved.

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

A decoding algorithm with an enhanced parity check matrix and a re-encoding scheme for LDPC codes is disclosed. The decoding algorithm includes the steps of: providing the enhanced parity check matrix; receiving a message part of an original codeword encoded by a generator matrix from the enhanced parity check matrix; setting a LLR for each bit node of the enhanced parity check matrix; processing hard decision on the message part of the original codeword; encoding the message part of the original codeword by the generator matrix to generate a new codeword having a generated parity part; comparing the original parity part with the generated parity part to find out bits of difference; voting candidate error bits to choose the most probably erratic bits; modifying LLR of the chosen bits to have a modified codeword; and processing a conventional iterative decoding procedure on the modified codeword to have a processed codeword.

Encoding and decoding systems are provided for reduced latency at the decoder. In the encode error detection codewords are produced from source bits. The error detection codewords are then encoded with a systematic error correction encoder to produce a set of parity bits. All of the systematic code source bits and at least some of the parity bits are mapped to modulation symbols for transmission. In the decoder, two signal processings are performed in parallel, one based on soft bit decisions and the other based on hard bit decisions. The soft bit decisions are processed using a systematic error correction decoder. The hard bit decisions are processed by re-encoding error detection codewords to produce parity bits. If the produced parity bits match received parity bits, then the hard bit decisions are reliable and are output without waiting for the result of the systematic error correction decoder.

A memory system includes a data channel, a controller configured to output a request across the data channel, and a memory device configured to store data and corresponding first parity, perform a decoding operation on the data to generate second parity in response to receipt of the request across the data channel, generate a difference from the first parity and the second parity, compress the difference, and enable the controller to access the data and the compressed difference to satisfy the request.

Disclosed in some examples are methods, systems, and machine-readable mediums for utilizing context information to create decoding feedback information to improve decoder accuracy and/or performance. In some examples, the context information is from layers of a network stack above the layers in which the decoders are present. The context information may be or be based upon information about previously received and decoded data and/or information about the sender to provide decoding feedback information to the decoder that is used either to correct a previous decoding error or to inform the decoder on which of a plurality of decoding choices is more likely to be correct. This may increase decoding performance by decreasing errors and in some examples, reducing the complexity of choices by eliminating certain decoding possibilities and thus increasing decoder efficiency.