A data processing method includes performing first equalization processing on a data stream that comprises a plurality of sub-data stream segments, performing segment de-interleaving on the data stream, separately performing first forward error correction (FEC) decoding on each sub-data stream segment in a data stream, performing, according to an equalization termination state of each sub-data stream segment, second equalization processing on each sub-data stream segment, performing second FEC decoding on the data stream, and outputting the data stream obtained according to the second FEC decoding in response to a preset iteration termination condition being met, or performing, in response to the preset iteration termination condition not being met, according to the equalization termination state of each sub-data stream segment obtained according to the first equalization, the second equalization processing on each sub-data stream segment obtained according to the second FEC decoding.

A decoding apparatus includes a multi-input branch metric calculation unit configured to calculate, by using a branch label corresponding to a path extending toward a state S at a time point N in a trellis diagram and a plurality of reception signal sequences, a branch metric in the state S, a path metric calculation unit configured to calculate a path metric in the state S at the time point N, and a surviving path list memory configured to store path labels corresponding to L path metrics among a plurality of calculated path metrics. The path metric calculation unit generates a path label in the state S at the time point N by combining the branch label with a path label in each of the states at the time point N−1 and the surviving path list memory outputs path labels corresponding to L path metrics.

A method of telecommunications includes the steps of receiving an encoded block having a plurality of values, dividing the received encoded block into a plurality of received segments, each received segment comprising at least two of the values, decoding each received segment by providing, for each received segment, a plurality of estimated encoded sequences, each estimated encoded sequence comprising at least two data units, merging estimated encoded sequences for consecutive segments to provide a plurality of candidate sequences, and selecting one of the plurality of candidate sequences by performing a closest fit calculation between the received encoded data block and each of the candidate sequences. The method is suitable for use in software-defined radios.

The disclosure provides a method and a polar code decoder for determining a to-be-flipped bit position when performing a successive cancellation list flip operation. The method includes: obtaining a polar code decoding tree generated by performing a successive cancellation list (SCL) operation on a polar code segment, and the polar code segment includes multiple bit positions, and each bit position in the polar code decoding tree includes multiple surviving paths and multiple pruned paths; in a post-processing stage for the SCL operation, estimating a correct path probability of each of the surviving paths and the pruned paths of the i-th bit position and accordingly estimating a reliability for the i-th bit position; selecting a specific bit position among the bit positions based on the reliability of each bit position; and performing an SCL flip operation on the polar code decoding tree based on the specific bit position.

A parity puncturing apparatus and method for fixed length signaling information are disclosed. A parity puncturing apparatus according to an embodiment of the present invention includes memory configured to provide a parity bit string for parity puncturing for the parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, and a processor configured to puncture a number of bits corresponding to a final puncturing size from the rear side of the parity bit string.

A parity puncturing apparatus and method for fixed length signaling information are disclosed. A parity puncturing apparatus according to an embodiment of the present invention includes memory configured to provide a parity bit string for parity puncturing for the parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, and a processor configured to puncture a number of bits corresponding to a final puncturing size from the rear side of the parity bit string.

The disclosure relates to generating a polar code and also to encoding and decoding data using a polar code. A method of generating a polar code includes obtaining a first matrix as an m-fold Kronecker product of a 2×2 binary lower triangular matrix where m=log2(M/2), M<N, and N is the length of a polar code to be generated. A second matrix may be obtained, where the inverse of the second matrix is a lower triangular band matrix. A transformation matrix may be generated for the polar code by calculating a Kronecker product of the second matrix with the first matrix. An information set I identifying reliable bit channels for the polar code may be determined. A polar codeword of length N may be obtained using the polar code that is decodable by iteratively applying a sliding decoding window of length M to the polar codeword.

A memory system includes a memory device and a controller. The memory device is configured to supply a read voltage into a plurality of non-volatile memory cells and transfer values obtained from the plural non-volatile memory cells. The controller is coupled to the memory device via at least one channel. The controller adjusts a level of the read voltage based on a cell difference probability (CDP) calculated from the values when a read operation to the plurality of non-volatile memory cells fails.

A decoding system, a decoding controller, and a decoding control method are provided. In the decoding system, a decoding controller is disposed between two adjacent decoders. The decoding controller determines whether to perform turn-off based on a non-turn-off indication received by a previous-stage decoder, a turn-off indication output by the previous-stage decoder, and historical turn-off probability statistics. This is equivalent to adding a buffer zone between the two adjacent decoders.

There is provided mechanisms for decoding an encoded sequence into a decoded sequence. A method is performed by an information decoder. The method comprises obtaining the encoded sequence. The encoded sequence has been encoded using a polar code. The method comprises successively decoding the encoded sequence into the decoded sequence. The decoding is performed for a given list size, LS, where LS>1, defining how many candidate decoded sequences in total the thus far decoded sequence is allowed to branch into during the decoding. The encoded sequence is decoded, until its first branching, by at least as many processing units in parallel as a factor, f, of the given list size. The factor is at least half the given list size, f≥LS/2.