Patent classifications
H03M13/39
Multidimensional multilevel coding encoder and decoder
A multidimensional multilevel coding (MLC) encoder comprises a soft forward error correction (FEC) encoder receiving first bits for generating soft FEC encoded bits, a redundancy generator receiving a subset of the soft FEC encoded bits for generating redundant bits, and a hard FEC encoder receiving second bits for generating hard FEC encoded bits. Combinations of the soft FEC encoded bits, the redundant bits, and the hard FEC encoded bits form labels for mapping to a plurality of constellation points. A MLC decoder comprises a redundancy decoder, a soft FEC decoder and a hard FEC decoder. The redundancy decoder combines log-likelihood-ratios (LLR) of soft FEC encoded bits received from the MLC encoder to allow the soft FEC decoder to produce decoded bits. Decoding of hard FEC encoded bits by the hard FEC decoder is conditioned on values of the bits decoded by the soft FEC decoder.
Receiver using pseudo partial response maximum likelihood sequence detection
Receivers and receiving methods having maximum likelihood sequence detection with pseudo partial response equalization. One illustrative receiver includes: a feedforward equalizer that produces an equalized receive signal by diminishing a receive signal's intersymbol interference; a decision element that derives initial symbol decisions from samples of the equalized receive signal; and a filter that applies a partial response to the equalized receive signal or to an equalization error signal to produce input for a maximum likelihood sequence detector (MLSD). The MLSD may be a reduced complexity detector that derives a final sequence of symbol decisions by evaluating state metrics only for each initial symbol decision and its competing symbol decision.
Asymmetric LLR generation using assist-read
A method of operating a storage system is provided. The storage system includes memory cells and a memory controller, wherein each memory cell is an m-bit multi-level cell (MLC), where m is an integer, and the memory cells are arranged in m pages. The method includes determining initial LLR (log likelihood ratio) values for each of the m pages, comparing bit error rates in the m pages, identifying a programmed state in one of the m pages that has a high bit error rate (BER), and selecting an assist-read threshold voltage of the identified page. The method also includes performing an assist-read operation on the identified page using the assist-read threshold voltage, determining revised LLR values for the identified page based on results from the assist-read operation, and performing soft decoding using the revised LLR values for the identified page and the initial LLR values for other pages.
Latency minimization for retransmissions in communications systems with multi-level coding and multi-level sequential demodulation and decoding and code block grouping from different component codes
Methods, systems, and devices for wireless communications employing multi-level coding with set partitioning on transmitting side and multi-level sequential decoding on the receiving side for latency minimization are described. In some systems, a transmitting device may transmit a code block group (CBG) to a receiving device including a first set of code blocks associated with a first decoding level and a second set of code blocks associated with a second decoding level. The receiving device may unsuccessfully decode one or more code blocks of the first set or the second set of code blocks and transmit a feedback message to the transmitting device. The transmitting device may determine that the data to be communicated via the CBG is latency-sensitive data and, as such, determine to retransmit both the first set and the second set of code blocks to the receiving device in response to receiving the feedback message.
Error recovery using adaptive LLR lookup table
Systems and methods are provided for performing error recovery using LLRs generated from multi-read operations. A method may comprise selecting a set of decoding factors for a multi-read operation to read a non-volatile storage device multiple times. The set of decoding factors may include a total number of reads, an aggregation mode for aggregating read results of multiple reads, and whether the read results include soft data. The method may further comprise issuing a command to the non-volatile storage device to read user data according to the set of decoding factors, generating a plurality of Log-Likelihood Ratio (LLR) values using a mapping engine from a pre-selected set of LLR value magnitudes based on the set of decoding factors, obtaining an aggregated read result in accordance with the aggregation mode and obtaining an LLR value from the plurality of LLR values using the aggregated read result as an index.
Deep Learning for Behavior-Based, Invisible Multi-Factor Authentication
Biometric behavior-based authentication may be enhanced by using convolutional deep neural networks to learn subject-specific features for each subject. The advantage is two-fold. First the need for a domain expert is eliminated, and the search space can be algorithmically explored. Second, the features that allow each subject to be differentiated from other subjects may be used. This allows the algorithm to learn the aspects of each subject that make them unique, rather than taking a set of fixed aspects and learning how those aspects are differentiated across subjects. The combined result is a far more effective authentication in terms of reduction of errors. Behavior-based, invisible multi-factor authentication (BIMFA) mays also automate the responses to authentication second and third factor requests (something you have and something you are). BIMFA leverages continuous, invisible behavioral biometrics on user devices to gain a continuous estimate of the authorization state of the user across multiple devices without requiring any explicit user interaction or input for authentication. As a result, BIMFA can demonstrate that a device is under the control of the authorized user without requiring any direct user interaction.
Using a pre-emption indication associated with a quasi co-location relationship
In some aspects, a user equipment (UE) may receive a configuration that indicates an association between a pre-emption indication field and at least one of: a set of transmission configuration indicator (TCI) states, a set of demodulation reference signal (DMRS) ports, or a set of layers; receive downlink control information (DCI) that includes a pre-emption indication that is indicated as a set of bits in the pre-emption indication field; determine whether the UE is scheduled to receive a communication in one or more pre-empted resources indicated by the set of bits, via a component carrier associated with the pre-emption indication, and using at least one of: a TCI state included in the set of TCI states, a DMRS port included in the set of DMRS ports, or a layer included in the set of layers; and decode the communication based at least in part on the determination.
ONE-SHOT STATE TRANSITION PROBABILITY ENCODER AND DECODER
A one-shot state transition decoder receives a codeword having N-bits. The decoder reads a first D-bits of the codeword to determine a stitching location d within the codeword. The stitching location identifies a start bit of unencoded data in the codeword. The codeword is decoded into an output buffer for user data of L bits, where N>L. Parameters of the decoder are set before the decoding, including setting a length of the codeword to N−L+d and a number of expected decoded bits to d. The decoding including decoding the d bits based on a set of state transition probabilities and copying decoded bits into the output buffer, the unencoded data being copied to the end of the output buffer.
PARAMETER ESTIMATION WITH MACHINE LEARNING FOR FLASH CHANNEL
Estimation of read parameters for a read channel of a solid-state storage device using a machine learning apparatus. The machine learning apparatus may be provided with signal count metrics from multiple regions of the memory cell signal space and syndrome weights from an error correction code. Other inputs may also be provided comprising metrics of the memory or read operations. In an example, the read parameters may include one or more reference threshold voltage values for read voltages applied to a memory cell and/or log-likelihood ratio (LLR) values for the memory cell.
Architecture for guessing random additive noise decoding (GRAND)
There is provided a method comprising, at a data receiver, receiving a channel codeword from a data sender over a noisy data channel, generating a plurality of candidate error patterns, the plurality of candidate error patterns comprising a plurality of one-bit error patterns and a plurality of multiple-bit error patterns generated from the plurality of one-bit error patterns, evaluating the plurality of candidate error patterns for codebook membership, based on the channel codeword, and outputting an estimated codeword when a codebook membership constraint is satisfied for a given candidate error pattern.