H03M13/43

Bit error rate estimation and classification in NAND flash memory

A method for reading data from an SSD, comprising: retrieving data from a target row of memory cells using initial threshold voltages; decoding the data using a first hard decision decoding stage; estimating a bit error rate (BER) of a target row of memory cells based on a distribution of threshold voltages of cells in a memory block containing the target row when the first hard decision decoding stage fails; classifying the BER of the target row based on a first BER threshold (BER-TH1); and executing a first read flow comprising at least one hard decision decoding stage if the BER is less than the BER-TH1, and executing a second read flow similar to the first read flow if the BER is greater than or equal to the BER-TH1, the second read flow skipping a hard decision decoding stage of the first read flow.

Storage parameters for a data storage device

A method of operating a data storage device having a memory includes reading error location data associated with a first region of the memory. The memory includes the first region and a second region. The method also includes generating one or more parameters based on the error location data. The method includes receiving data to be written to the memory and encoding the data to produce a codeword. The method also includes partitioning the codeword based on the one or more parameters to generate a first portion and a second portion. The method further includes performing a write operation to store the first portion at the first region and to store the second portion at the second region.

SYNDROME CHECK FUNCTIONALITY TO DIFFERENTIATE BETWEEN ERROR TYPES
20250047304 · 2025-02-06 ·

Methods, systems, and devices for syndrome check functionality to differentiate between error types are described. A host system, a memory system, or some combination of both may include syndrome check circuitry to provide enhanced error diagnostic capabilities for data communicated between the host system and the memory system. The syndrome check circuitry may receive a first signal from the memory system indicating whether the memory system detected and attempted to correct an error in the data and may receive a second signal from the host system indicating whether the host system detected an error in the received data. The syndrome check circuitry may compare the first signal and the second signal using a set of logic gates to differentiate between different combinations of errors detected at one or both of the memory system or the host system.

SYNDROME CHECK FUNCTIONALITY TO DIFFERENTIATE BETWEEN ERROR TYPES
20250047304 · 2025-02-06 ·

Methods, systems, and devices for syndrome check functionality to differentiate between error types are described. A host system, a memory system, or some combination of both may include syndrome check circuitry to provide enhanced error diagnostic capabilities for data communicated between the host system and the memory system. The syndrome check circuitry may receive a first signal from the memory system indicating whether the memory system detected and attempted to correct an error in the data and may receive a second signal from the host system indicating whether the host system detected an error in the received data. The syndrome check circuitry may compare the first signal and the second signal using a set of logic gates to differentiate between different combinations of errors detected at one or both of the memory system or the host system.

RELIABLE DATA READING WITH DATA SET SCREENING BY ERROR INJECTION
20170125053 · 2017-05-04 ·

According to one embodiment, a system for processing data includes a controller configured to determine whether a position error signal (PES) is invalid while reading data from a magnetic medium using at least one data channel. The controller is also configured to determine whether a PES value is above a first predetermined threshold in response to a determination that the PES is valid. Moreover, the controller is configured to inject error bits into a data stream in place of corresponding bits of decoded data in response to a determination that the PES is invalid and in response to a determination that the PES value is above the first predetermined threshold. Other systems and methods for processing data are described in accordance with more embodiments.

Data Unit Retransmission
20170104556 · 2017-04-13 ·

A source node may send a first data unit to a destination node. To send the first data unit, the source node may transmit a modulation pattern over a transmission medium. In some cases, particular data units may correspond to modulation patterns with features that cause errors in transmission. The source node may receive an indication of an error from the destination node. To avoid repeated errors the retransmission, coding circuitry at the source node may alter data within the first data unit to generate a retransmission data unit. The alteration may result in the retransmission data unit corresponding to a modulation pattern different from that of the first data unit. The new modulation pattern may lack the error causing features and reduce the chance of repeated errors.

Memory system
09607703 · 2017-03-28 · ·

According to one embodiment, a memory system includes a memory and a setting unit. The memory includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory cells, each of which holds an electrical charge. The peripheral circuit is configured to read a value from each memory cell by comparing a quantity of an electrical charge held in the memory cell with a determination threshold. The memory stores first data in the memory cell array. The first data include a plurality of values. The setting unit is configured to change the determination threshold according to the number of values which are different in second data and third data among the plurality of values. The second data are first data before being written to the memory. The third data are first data that have been read from the memory.

Reliable data reading with data set screening by error injection

According to one embodiment, a method for processing data includes determining whether a PES is invalid while reading data from a magnetic medium using at least one data channel, determining whether a PES value is above a first predetermined threshold when the PES is valid, injecting error bits into a data stream in place of corresponding bits of decoded data when the PES is invalid and/or the PES value is above the first predetermined threshold, decoding the data using a run-length limited (RLL) decoder to produce the decoded data based on the data from the magnetic medium, and outputting the data stream. Other methods, systems, and tape drives for processing data using error injection are described in more embodiments.

Reliable data reading with data set screening by error injection

According to one embodiment, a method for processing data includes determining whether a PES is invalid while reading data from a magnetic medium using at least one data channel, determining whether a PES value is above a first predetermined threshold when the PES is valid, injecting error bits into a data stream in place of corresponding bits of decoded data when the PES is invalid and/or the PES value is above the first predetermined threshold, decoding the data using a run-length limited (RLL) decoder to produce the decoded data based on the data from the magnetic medium, and outputting the data stream. Other methods, systems, and tape drives for processing data using error injection are described in more embodiments.

Universal error-correction circuit with fault-tolerant nature, and decoder and triple modular redundancy circuit that apply it

A universal error-correction circuit with fault-tolerant nature includes an error-correction unit with fault-tolerant nature implemented by a logic gate, where digital input signals of the error-correction unit with fault-tolerant nature are separately I.sub.0, I.sub.1 . . . , I.sub.2k-1, and I.sub.2k, digital output signals of the error-correction unit with fault-tolerant nature are separately O.sub.0, O.sub.1, . . . , O.sub.k-2, and O.sub.k-1, and the digital input signals and the digital output signals belong to a set {0,1}, where k is a positive integer. The error-correction unit with fault-tolerant nature is configured to, when k=1, set O.sub.0=I.sub.0 if I.sub.0=I.sub.1, and O.sub.0=I.sub.2 otherwise; and when k>1, set O.sub.k-1=I.sub.2k-1 if O.sub.k-2=I.sub.2k-1, and O.sub.k-1=I.sub.2k otherwise. Because a logical relationship between input and output is uniquely certain, the error-correction circuit with fault-tolerant nature may be implemented only by a logic gate.