Universal error-correction circuit with fault-tolerant nature, and decoder and triple modular redundancy circuit that apply it

Abstract

A universal error-correction circuit with fault-tolerant nature includes an error-correction unit with fault-tolerant nature implemented by a logic gate, where digital input signals of the error-correction unit with fault-tolerant nature are separately I.sub.0, I.sub.1 . . . , I.sub.2k-1, and I.sub.2k, digital output signals of the error-correction unit with fault-tolerant nature are separately O.sub.0, O.sub.1, . . . , O.sub.k-2, and O.sub.k-1, and the digital input signals and the digital output signals belong to a set {0,1}, where k is a positive integer. The error-correction unit with fault-tolerant nature is configured to, when k=1, set O.sub.0=I.sub.0 if I.sub.0=I.sub.1, and O.sub.0=I.sub.2 otherwise; and when k>1, set O.sub.k-1=I.sub.2k-1 if O.sub.k-2=I.sub.2k-1, and O.sub.k-1=I.sub.2k otherwise. Because a logical relationship between input and output is uniquely certain, the error-correction circuit with fault-tolerant nature may be implemented only by a logic gate.

Claims

1. A universal error-correction circuit with fault-tolerant nature, comprising: an error-correction unit with fault-tolerant nature implemented by a logic gate, wherein digital input signals of the error-correction unit with fault-tolerant nature are separately I.sub.0, I.sub.1 . . . , I.sub.2k-1, and I.sub.2k, wherein a number of the digital input signals that exist in the universal error-correction circuit with fault-tolerant nature is 2k+1, wherein digital output signals of the error-correction unit with fault-tolerant nature are separately O.sub.0, O.sub.1 . . . , O.sub.k-2, and O.sub.k-1, wherein a number of the digital output signals that exist in the universal error-correction circuit with fault-tolerant nature is k, wherein the digital input signals and the digital output signals belong to a set {0,1}, wherein k is a positive integer, wherein the error-correction unit with fault-tolerant nature is configured to: set O.sub.0=I.sub.0 when k=1 and I.sub.0=I.sub.1; set O.sub.0=I.sub.2 when I.sub.0 is not equal to I.sub.1; set O.sub.k-1=I.sub.2k-1 when k>1 and O.sub.k-2=I.sub.2k-1; and set O.sub.k-1=I.sub.2k when O.sub.k-1 is not equal to I.sub.2k-1, wherein when k=3 in the error-correction unit with fault-tolerant nature, seven corresponding digital input signals are separately I.sub.0, I.sub.1, I.sub.2, I.sub.3, I.sub.4, I.sub.5, and I.sub.6, and three corresponding digital output signals are separately O.sub.0, O.sub.1, and O.sub.2, wherein the error-correction unit with fault-tolerant nature comprises three error-correction subunits with fault-tolerant nature, which are separately a first error-correction subunit with fault-tolerant nature, a second error-correction subunit with fault-tolerant nature, and a third error-correction subunit with fault-tolerant nature, each error-correction subunit with fault-tolerant nature is corresponding to three digital input signals and one digital output signal, and each error-correction subunit with fault-tolerant nature comprises a first AND gate, a first OR gate, a second AND gate, and a second OR gate, wherein two input signals of both the first AND gate and the first OR gate are a first digital input signal and a second digital input signal, one input signal of the second AND gate is a third digital input signal, the other input signal of the second AND gate is an output signal of the first OR gate, and an output signal of the second AND gate and an output signal of the first AND gate serve as two input signals of the second OR gate, wherein a first digital input signal, a second digital input signal, and a third digital input signal of the first error-correction subunit with fault-tolerant nature are I.sub.0, I.sub.1, and I.sub.2, respectively, and an output signal of the first error-correction subunit with fault-tolerant nature is O.sub.0, wherein a first digital input signal, a second digital input signal, and a third digital input signal of the second error-correction subunit with fault-tolerant nature are I.sub.3, I.sub.4, and O.sub.0, respectively, and an output signal of the second error-correction subunit with fault-tolerant nature is O.sub.1, and wherein a first digital input signal, a second digital input signal, and a third digital input signal of the third error-correction subunit with fault-tolerant nature are I.sub.5, I.sub.6, and O.sub.1, respectively, and an output signal of the third error-correction subunit with fault-tolerant nature is O.sub.2.

2. The universal error-correction circuit with fault-tolerant nature according to claim 1, wherein the universal error-correction circuit with fault-tolerant nature comprises a universal decoder.

3. The universal error-correction circuit with fault-tolerant nature according to claim 2, wherein the universal decoder comprises a variable node circuit, an interleaver, a check node circuit, and a de-interleaver.

4. The universal error-correction circuit with fault-tolerant nature according to claim 3, wherein the variable node circuit comprises the universal error-correction circuit with fault-tolerant nature.

5. The universal error-correction circuit with fault-tolerant nature according to claim 3, wherein the interleaver is configured to randomly shuffle a received information sequence, read the randomly shuffled information sequence from front to back, and send the read information sequence to the check node circuit.

6. The universal error-correction circuit with fault-tolerant nature according to claim 3, wherein the check node circuit is configured to calculate external information output by the variable node circuit to obtain an information value of a check node.

7. The universal error-correction circuit with fault-tolerant nature according to claim 3, wherein the check node circuit comprises an exclusive-OR gate circuit.

8. The universal error-correction circuit with fault-tolerant nature according to claim 3, wherein the de-interleaver is configured to randomly shuffle an information sequence and arrange the randomly shuffled information sequence from back to front.

9. A universal error-correction circuit with fault-tolerant nature, comprising: an error-correction unit with fault-tolerant nature implemented by a logic gate, wherein digital input signals of the error-correction unit with fault-tolerant nature are separately I.sub.0, I.sub.1 . . . , I.sub.2k-1, and I.sub.2k, wherein digital output signals of the error-correction unit with fault-tolerant nature are separately O.sub.0, O.sub.1 . . . , O.sub.k-2, and I.sub.k-1, wherein the digital input signals and the digital output signals belong to a set {0,1}, wherein k is a positive integer, and wherein the error-correction unit with fault-tolerant nature is configured to: set O.sub.0=I.sub.0 when k=1 and I.sub.0=I.sub.1; set O.sub.0=I.sub.2 when I.sub.0 is not equal to I.sub.1; set O.sub.k-1=I.sub.2k-1 when k>1 and O.sub.k-2=I.sub.2k-1; and set O.sub.k-1=I.sub.2k when O.sub.k-1 is not equal to I.sub.2k-1, wherein when k=3 in the error-correction unit with fault-tolerant nature, seven corresponding digital input signals are separately I.sub.0, I.sub.1, I.sub.2, I.sub.3, I.sub.4, I.sub.5, and I.sub.6, and three corresponding digital output signals are separately O.sub.0, O.sub.1, and O.sub.2, wherein the error-correction unit with fault-tolerant nature comprises three error-correction subunits with fault-tolerant nature, which are separately a first error-correction subunit with fault-tolerant nature, a second error-correction subunit with fault-tolerant nature, and a third error-correction subunit with fault-tolerant nature, each error-correction subunit with fault-tolerant nature is corresponding to three digital input signals and one digital output signal, and each error-correction subunit with fault-tolerant nature comprises a first AND gate, a first OR gate, a second AND gate, and a second OR gate, wherein two input signals of both the first AND gate and the first OR gate are a first digital input signal and a second digital input signal, one input signal of the second AND gate is a third digital input signal, the other input signal of the second AND gate is an output signal of the first OR gate, and an output signal of the second AND gate and an output signal of the first AND gate serve as two input signals of the second OR gate, wherein a first digital input signal, a second digital input signal, and a third digital input signal of the first error-correction subunit with fault-tolerant nature are I.sub.0, I.sub.1, and I.sub.2, respectively, and an output signal of the first error-correction subunit with fault-tolerant nature is O.sub.0, wherein a first digital input signal, a second digital input signal, and a third digital input signal of the second error-correction subunit with fault-tolerant nature are I.sub.3, I.sub.4, and O.sub.0, respectively, and an output signal of the second error-correction subunit with fault-tolerant nature is O.sub.1, and wherein a first digital input signal, a second digital input signal, and a third digital input signal of the third error-correction subunit with fault-tolerant nature are I.sub.5, I.sub.6, and O.sub.1, respectively, and an output signal of the third error-correction subunit with fault-tolerant nature is O.sub.2.

10. The universal error-correction circuit with fault-tolerant nature according to claim 9, wherein the universal error-correction circuit with fault-tolerant nature comprises a universal decoder.

11. The universal error-correction circuit with fault-tolerant nature according to claim 10, wherein the universal decoder comprises a variable node circuit, an interleaver, a check node circuit, and a de-interleaver.

12. The universal error-correction circuit with fault-tolerant nature according to claim 11, wherein the variable node circuit comprises the universal error-correction circuit with fault-tolerant nature.

13. The universal error-correction circuit with fault-tolerant nature according to claim 11, wherein the interleaver is configured to randomly shuffle a received information sequence, read the randomly shuffled information sequence from front to back, and send the read information sequence to the check node circuit.

14. The universal error-correction circuit with fault-tolerant nature according to claim 11, wherein the check node circuit is configured to calculate external information output by the variable node circuit to obtain an information value of a check node.

15. The universal error-correction circuit with fault-tolerant nature according to claim 11, wherein the check node circuit comprises an exclusive-OR gate circuit.

16. The universal error-correction circuit with fault-tolerant nature according to claim 11, wherein the de-interleaver is configured to randomly shuffle an information sequence and arrange the randomly shuffled information sequence from back to front.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) To describe the technical solutions in the embodiments of the present invention or in the prior art more clearly, the following briefly introduces the accompanying drawings required for describing the embodiments or the prior art. The accompanying drawings in the following description show merely some embodiments of the present invention, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.

(2) FIG. 1 is a schematic diagram of fault-tolerance of triple modular redundancy in the prior art;

(3) FIG. 2 is a schematic diagram of Embodiment 1 of a universal error-correction circuit with fault-tolerant nature according to the present invention;

(4) FIG. 3 is a schematic diagram of an error-correction circuit with fault-tolerant nature where k=1 according to the present invention;

(5) FIG. 4 is a schematic diagram of an error-correction circuit with fault-tolerant nature where k=2 according to the present invention;

(6) FIG. 5 is a schematic diagram of Embodiment 2 of an error-correction circuit with fault-tolerant nature according to the present invention;

(7) FIG. 6 is a schematic diagram of Embodiment 3 of an error-correction circuit with fault-tolerant nature according to the present invention;

(8) FIG. 7 is a schematic diagram of Embodiment 1 of a decoder according to the present invention;

(9) FIG. 8 is a schematic diagram of Embodiment 2 of a decoder according to the present invention;

(10) FIG. 9 is a schematic diagram of simulation of a decoder according to the present invention; and

(11) FIG. 10 is a circuit diagram of a triple modular redundancy circuit according to the present invention.

DESCRIPTION OF EMBODIMENTS

(12) It should be noted that a universal error-correction circuit with fault-tolerant nature provided by an embodiment of the present invention includes an error-correction unit with fault-tolerant nature implemented by a logic gate, where digital input signals of the error-correction unit with fault-tolerant nature are separately I.sub.0, I.sub.1 . . . , I.sub.2k-1, and I.sub.2k, digital output signals of the error-correction unit with fault-tolerant nature are separately O.sub.0, O.sub.1 . . . , O.sub.k-2, and O.sub.k-1, and the digital input signals and the digital output signals belong to a set {0,1}, where k is a positive integer. The error-correction unit with fault-tolerant nature is configured to, when k=1, set O.sub.0=I.sub.0 if I.sub.0=I.sub.1, and O.sub.0=I.sub.2 otherwise; and when k>1, set O.sub.k-1=I.sub.2k-1 if O.sub.k-2=I.sub.2k-1, and O.sub.k-1=I.sub.2k otherwise.

(13) The following clearly describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. The described embodiments are merely a part rather than all of the embodiments of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

(14) To make the foregoing objectives, features, and advantages of the present invention more evident and comprehensible, the following describes specific implementation manners of the present invention in details with reference to the accompanying drawings.

Embodiment 1

(15) Referring to FIG. 2, the figure is a schematic structural diagram of a universal error-correction circuit with fault-tolerant nature according to the present invention.

(16) The universal error-correction circuit with fault-tolerant nature provided by this embodiment includes an error-correction unit 100 with fault-tolerant nature implemented by a logic gate.

(17) Digital input signals of the error-correction unit 100 with fault-tolerant nature are separately I.sub.0, I.sub.1 . . . , I.sub.2k-1, and I.sub.2k, digital output signals of the error-correction unit 100 with fault-tolerant nature are separately O.sub.0, O.sub.1 . . . , O.sub.k-2, and O.sub.k-1, and the digital input signals and the digital output signals belong to a set {0,1}, where k is a positive integer.

(18) The error-correction unit 100 with fault-tolerant nature is configured to, when k=1, set O.sub.0=I.sub.0 if I.sub.0=I.sub.1, and O.sub.0=I.sub.2 otherwise; and when k>1, set O.sub.k-1=I.sub.2k-1 if O.sub.k-2=I.sub.2k-1, and O.sub.k-1=I.sub.2k otherwise.

(19) To make a person skilled in the art better understand the technical solutions of the present invention, the following separately takes k=1 and k=2 as examples for description.

(20) Referring to FIG. 3, the figure is a schematic diagram of an error-correction circuit with fault-tolerant nature where k=1 according to the present invention.

(21) In the error-correction circuit with fault-tolerant nature corresponding to FIG. 3, k=1, that is, three corresponding digital input signals are I.sub.0, I.sub.1, and I.sub.2, and one digital output signal is O.sub.0.

(22) A truth table of the digital input signals and the digital output signal that are corresponding to FIG. 3 is shown by Table 1.

(23) TABLE-US-00001 TABLE 1 Input Output I.sub.0 I.sub.1 I.sub.2 O.sub.0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 1 1 1 1 0 1 1 1 1 1 1

(24) The following introduces a case in which k=2 with reference to FIG. 4 and Table 2.

(25) Referring to FIG. 4, the figure is a schematic diagram of an error-correction circuit with fault-tolerant nature where k=2 according to the present invention.

(26) In the error-correction circuit with fault-tolerant nature corresponding to FIG. 4, k=2, that is, five corresponding digital input signals are I.sub.0, I.sub.1, I.sub.2, I.sub.3, and I.sub.4, and two digital output signals are O.sub.0, and O.sub.1.

(27) A truth table of the digital input signals and the digital output signals that are corresponding to FIG. 4 is shown by Table 2.

(28) TABLE-US-00002 TABLE 2 Input Output I.sub.0 I.sub.1 I.sub.2 I.sub.3 I.sub.4 O.sub.0 O.sub.1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 1 0 0 1 0 1 0 0 0 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 0 1 1 1 0 0 0 1 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1

(29) It can be obtained, by analysis according to FIG. 3, FIG. 4, Table 1, and Table 2, that no matter k=1 or k=2, the error-correction unit with fault-tolerant nature meets that when k=1, O.sub.0=I.sub.0 if I.sub.0=I.sub.1, and O.sub.0=I.sub.2 otherwise; and when k>1, O.sub.k-1=I.sub.2k-1 if O.sub.k-2=I.sub.2k-1, and O.sub.k-1=I.sub.2k otherwise.

(30) It can be understood that an error-correction circuit with fault-tolerant nature provided by the present invention is provided with general commonality of application, and a specific function is determined by a digital input signal and a digital output signal. Because there is a unique certainty between input and output that are of the error-correction circuit with fault-tolerant nature, any circuit that meets a relationship between the input and output that are of the error-correction circuit with fault-tolerant nature provided by the present invention falls within the protection scope of the present invention. It can be understood that, because a logical relationship between the input and the output is uniquely certain, the error-correction circuit with fault-tolerant nature may be implemented only by a logic gate. There may be a plurality of specific implementation manners, as long as input and output meet the uniquely certain logical relationship of the present invention. Therefore, the error-correction circuit with fault-tolerant nature provided by the present invention is provided with general commonality.

(31) The following introduces a specific internal implementation circuit of an error-correction circuit with fault-tolerant nature provided by an embodiment of the present invention with reference to the accompanying drawings.

Embodiment 2

(32) Referring to FIG. 5, the figure is a schematic diagram of Embodiment 2 of an error-correction circuit with fault-tolerant nature provided by the present invention.

(33) In the error-correction unit with fault-tolerant nature provided by this embodiment, when k=1, three corresponding digital input signals are separately I.sub.0, I.sub.1, and I.sub.2; and one corresponding digital output signal is O.sub.0.

(34) The error-correction unit with fault-tolerant nature includes a first AND gate A1, a first OR gate B1, a second AND gate A2, and a second OR gate B2.

(35) Two input signals of the first OR gate B1 are separately I.sub.0 and I.sub.1.

(36) Two input signals of the first AND gate A1 are separately I.sub.0 and I.sub.1.

(37) One input signal of the second AND gate A2 is I.sub.2, and an output signal of the first OR gate B1 serves as the other input signal of the second AND gate A2.

(38) An output signal of the second AND gate A2 and an output signal of the first AND gate A1 serve as two input signals of the second OR gate B2.

(39) An output signal of the second OR gate B2 serves as the output signal O.sub.0 of the error-correction unit with fault-tolerant nature.

(40) From a relationship between the logic gates in the circuit in FIG. 5, it can be obtained that a relationship between input and output meets a truth table shown by Table 1.

Embodiment 3

(41) FIG. 5 shows a circuit implementation manner where k=1, and the following introduces a circuit implementation manner where k=3 with reference to FIG. 6.

(42) Referring to FIG. 6, the figure is a schematic diagram of Embodiment 3 of an error-correction circuit with fault-tolerant nature provided by the present invention.

(43) In this embodiment, when k=3 in the error-correction unit with fault-tolerant nature, seven corresponding digital input signals are separately: I.sub.0, I.sub.1, I.sub.2, I.sub.3, I.sub.4, I.sub.5, and I.sub.6; and three corresponding digital output signals are separately: O.sub.0, O.sub.1, and O.sub.2.

(44) The error-correction unit with fault-tolerant nature includes three error-correction subunits with fault-tolerant nature, which are separately a first error-correction subunit 100a with fault-tolerant nature, a second error-correction subunit 100b with fault-tolerant nature, and a third error-correction subunit 100c with fault-tolerant nature. Each error-correction subunit with fault-tolerant nature is corresponding to three digital input signals and one digital output signal; and each error-correction subunit with fault-tolerant nature includes a first AND gate A1, a first OR gate B1, a second AND gate A2, and a second OR gate B2.

(45) Two input signals of both the first AND gate A1 and the first OR gate B1 are a first digital input signal and a second digital input signal; one input signal of the second AND gate A2 is a third digital input signal; the other input signal of the second AND gate A2 is an output signal of the first OR gate B2; and an output signal of the second AND gate A2 and an output signal of the first AND gate A1 serve as two input signals of the second OR gate B2.

(46) A first digital input signal, a second digital input signal, and a third digital input signal of the first error-correction subunit 100a with fault-tolerant nature are I.sub.0, I.sub.1, and I.sub.2, respectively; and an output signal of the first error-correction subunit 100a with fault-tolerant nature is O.sub.0.

(47) A first digital input signal, a second digital input signal, and a third digital input signal of the second error-correction subunit 100b with fault-tolerant nature are I.sub.3, I.sub.4, and O.sub.0, respectively; and an output signal of the second error-correction subunit 100b with fault-tolerant nature is O.sub.1.

(48) A first digital input signal, a second digital input signal, and a third digital input signal of the third error-correction subunit 100c with fault-tolerant nature are I.sub.5, I.sub.6, and O.sub.1, respectively; and an output signal of the third error-correction subunit 100c with fault-tolerant nature is O.sub.2.

(49) From a relationship between the logic gates in the circuit shown in FIG. 6, it can be obtained that a logical relationship between input and output meets a correspondence, between input and output, defined in Embodiment 1 of the present invention.

(50) Based on the error-correction circuit with fault-tolerant nature provided by the foregoing embodiments, the present invention further provides a decoder which is implemented by using the error-correction circuit with fault-tolerant nature. Detailed introduction is provided below with reference to the accompanying drawings.

Embodiment 1 of a Decoder

(51) Referring to FIG. 7, the figure is a schematic diagram of Embodiment 1 of a decoder according to the present invention.

(52) The universal decoder provided by this embodiment includes a variable node module 704, an interleaver 701, a check node module 702, and a de-interleaver 703.

(53) The variable node module 704 includes the universal error-correction circuit with fault-tolerant nature described in the foregoing embodiments.

(54) The interleaver 701 is configured to randomly shuffle a received information sequence, then read the randomly shuffled information sequence from front to back, and send the read information sequence to the check node module 702.

(55) The check node module 702 is configured to calculate external information output by the variable node module 704 to obtain an information value of a check node.

(56) It should be noted that the check node module 702 may be implemented by an exclusive-OR gate circuit.

(57) The de-interleaver 703 is configured to randomly shuffle an information sequence, and then arrange the randomly shuffled information sequence from back to front.

(58) The variable node module 704 is configured to calculate external information output by the check node module 702 to obtain an information value of a variable node.

(59) The variable node module 704 in the decoder provided by this embodiment may be implemented by the error-correction circuit with fault-tolerant nature provided by the foregoing embodiments of the present invention. By applying the error-correction circuit with fault-tolerant nature provided by the embodiments of the present invention, not only a decoding function may be implemented in the decoder, but also a fault-tolerant function may be implemented in the decoder.

Embodiment 2 of a Decoder

(60) The following introduces in detail application of an error-correction circuit with fault-tolerant nature, provided by the present invention, in a decoder with reference to a specific embodiment.

(61) Referring to FIG. 8, the figure is a schematic diagram of Embodiment 2 of a decoder according to the present invention.

(62) In this embodiment, introduction is provided by using an example in which a weight of a variable node of a decoder is three. Further, the number of times of iterative decoding used by the decoder is three, and an circuit for performing iteration is not implemented by using a form of a counter circuit, but is implemented by directly using an error-correction circuit with fault-tolerant nature provided by the present invention, that is, the circuit for performing iteration is constructed by directly using a logic gate circuit. Details may be referred to a logic gate circuit shown in FIG. 8.

(63) In FIG. 8, a represents a parameter of a binary symmetric channel (BSC).

(64) In FIG. 8, three error-correction circuits with fault-tolerant nature are included.

(65) It can be seen that internal structures of the three error-correction circuits with fault-tolerant nature are the same. Each error-correction circuit with fault-tolerant nature further includes three error-correction units with fault-tolerant nature inside, and internal structures of the three error-correction units with fault-tolerant nature are also the same, and the three error-correction units with fault-tolerant nature include same logic gates.

(66) In a BSC simulation environment, a decoder circuit shown in FIG. 8 is configured to decode low density parity check code (LDPC). For example, LDPC (3, 6), [s, r] with a code length of 64, where s represents a source code byte part of a code word, r represents a redundancy byte part of the code word, 3 represents that a weight of a variable node in the decoder is 3, and 6 represents that a weight of a check node in the decoder is 6.

(67) For a simulation result, reference may be made to FIG. 9, and the figure is a schematic diagram of simulation of a decoder according to the present invention.

(68) A frame error rate (FER) of information received from a noisy channel is represented by an X axis in FIG. 9.

(69) A decoding circuit in FIG. 8 is used, and in a BSC noisy channel simulation environment, (3, 6) LDPC code of a code length of 64 is used, [s, r], where s represents a source code byte part of a code word, and r represents a redundancy byte part of the code word, so as to perform the simulation. An FER of information received from the noisy channel is represented by the X axis in FIG. 9. In addition, noise of the BSC noisy channel is added to the decoding circuit shown in FIG. 8 to server as internal noise (Internal Error) of the decoding circuit, and a hard error is added to the source code byte part of the code word, so as to simulate a hard error rate of the simulation circuit.

(70) A Y axis shown in FIG. 9 represents information that is generated after decoding and output by a decoder, where the decoder is based on an error-correction circuit with fault-tolerant nature, shown in FIG. 8, provided by the present invention.

(71) It can be seen from FIG. 9 that when a frame error rate of input is close to 0.5, a frame error rate of output after decoding reduces to a level close to 10.sup.3. Therefore, it can be seen that, by using a decoder including an error-correction circuit with fault-tolerant nature and provided by the present invention, and in an environment where the decoder has internal noise, a fault-tolerance and error-correction capability of the decoder has at least two orders of magnitude of error-correction performance.

(72) In this embodiment, the decoder is configured to decode LDPC code. It can be understood that the decoder may decode many types of code, and no more examples are provided one by one in this embodiment of the present invention.

(73) It can be seen from the foregoing analysis that a decoder provided by the present invention has a fast decoding speed, where only three times of decoding are needed to meet a requirement. However, a decoder in the prior art generally needs up to 20 times of decoding to meet the requirement. In addition, a fault-tolerance and error-correction capability of the decoder provided by the embodiment is extremely strong, and the fault-tolerance and error-correction capability of the decoder has at least two orders of magnitude of error-correction performance. It should be noted that the decoder, shown in FIG. 8, is a specific application example of an error-correction unit with fault-tolerant nature provided by the present invention. It can be understood that the error-correction unit with fault-tolerant nature provided by the embodiment of the present invention may not only be applied in a decoder, but may be applied in many other circuits.

(74) Based on the error-correction circuit with fault-tolerant nature provided by the foregoing embodiments, the present invention further provides a triple modular redundancy circuit which is implemented by applying the error-correction circuit with fault-tolerant nature. Detailed introduction is provided below with reference to the accompanying drawings.

(75) Referring to FIG. 10, the figure is a schematic diagram of a triple modular redundancy circuit according to the present invention.

(76) The triple modular redundancy circuit totally includes three digital input signals, which are separately I.sub.1, I.sub.2, and I.sub.3, and one digital output signal O.sub.0.

(77) It can be seen from FIG. 10 that the triple modular redundancy circuit includes six error-correction units with fault-tolerant nature, and each error-correction unit with fault-tolerant nature is also implemented by the logic gate circuit shown in FIG. 5.

(78) The error-correction unit with fault-tolerant nature includes: a first AND gate A1, a first OR gate B1, a second AND gate A2, and a second OR gate B2.

(79) Two input signals of the first OR gate B1 are separately I.sub.1 and I.sub.2.

(80) Two input signals of the first AND gate A1 are separately I.sub.1 and I.sub.2.

(81) One input signal of the second AND gate A2 is I.sub.3, and an output signal of the first OR gate B1 serves as the other input signal of the second AND gate A2.

(82) An output signal of the second AND gate A2 and an output signal of the first AND gate A1 serve as two input signals of the second OR gate B2.

(83) An output signal of the second OR gate B2 serves as the output signal O.sub.0 of the error-correction unit with fault-tolerant nature.

(84) It should be noted that a voter in the triple modular redundancy circuit is implemented by a circuit in FIG. 10 provided by the present invention.

(85) In FIG. 1, three functions simultaneously execute a same operation. Output of the three functions serves as input of a voter; and the voter takes same output that is in the majority as correct output of a voting system, which is usually called two out of three.

(86) As long as two same errors do not occur in the three functions simultaneously, an error of a faulty function may be concealed, so that correct system output is ensured. Because the three functions are independent of each other, a case where two functions have errors simultaneously is of an extremely small probability, so that system reliability may be greatly increased.

(87) A function of the voter is implemented by the circuit provided in FIG. 10, and in a case in which there is an internal error, an extremely strong error-correction capability may be achieved.

(88) A truth table of triple modular redundancy shown in FIG. 10 is as what is shown by Table 1, except that three input signals are I.sub.1, I.sub.2, and I.sub.3, and an output signal is O.sub.0. From the truth table shown by Table 1, it can be seen that a working principle of the voter in the triple modular redundancy circuit is a principle of two out of three where the majority prevails against the minority, that is, an output result of a whole system is determined by same output that is in the majority. When there are two input signals that are 0, the output result is 0; and when there are two input signals that are 1, the output result is 1. Consequently, a desirable fault-tolerant function is implemented.

(89) It should be noted that the foregoing embodiments are introduced by using examples in which an error-correction circuit with fault-tolerant nature, provided by the embodiments of the present invention, is applied in a decoder and in a triple modular redundancy circuit. In addition, the error-correction circuit with fault-tolerant nature provided by the embodiments of the present invention may not only be applied in the forgoing circuits, but may be applied in many other circuits, for example, may be applied in an adder which needs fault-tolerance.

(90) Specifically, three architectures shown in FIG. 6 may be used to implement a binary adder with a fault-tolerant function, which may at least correct one error digit of output.

(91) The foregoing descriptions are merely exemplary embodiments of the present invention, but are not intended to limit any form of the present invention. Although the present invention has been disclosed above with the exemplary embodiments, the exemplary embodiments are not intended to limit the present invention. Any person skilled in the art may, without departing from the scope of the technical solutions of the present invention, make a number of possible variations or modifications to the technical solutions of the present invention by using the foregoing disclosed methods and technical content, or amend the technical solutions of the present invention to an equivalent embodiment that is an equivalent variation. Therefore, any simple amendment, equivalent variation and modification that are made to the foregoing embodiments according to technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.