According to one embodiment, a memory controller includes an encoding unit that generates a first code word, a duplication unit that duplicates the first code word, a memory interface that writes a code word group including the first code word and code words being duplicates of the first code word into a non-volatile memory, and reads the code words forming the code word group from the non-volatile memory, a determination unit that obtains a result of majority decision using the first code word and the plurality of code words, which are included in the code word group read from the non-volatile memory, and a decoding unit that decodes a code word being the result of the majority decision and corrects an error.

A communication device includes a data source that generates data for transmission over a bus, and that further includes a data encoder coupled to receive and encode outgoing data. The encoder further includes a coupling toggle rate (CTR) calculator configured to calculate a CTR for the outgoing data, a threshold calculator configured to determine an expected value of the CTR as a threshold value, a comparator configured to compare the calculated CTR to the threshold value wherein the comparison is used to determine whether to perform an encoding step by an encoding block configured to selectively encode said data. A method according to one embodiment includes determining and comparing a CTR and an expected CTR to determine whether to encode the outgoing data. Any one of a plurality different coding techniques may be used including bus inversion.

A communication device includes a data source that generates data for transmission over a bus, and that further includes a data encoder coupled to receive and encode outgoing data. The encoder further includes a coupling toggle rate (CTR) calculator configured to calculate a CTR for the outgoing data, a threshold calculator configured to determine an expected value of the CTR as a threshold value, a comparator configured to compare the calculated CTR to the threshold value wherein the comparison is used to determine whether to perform an encoding step by an encoding block configured to selectively encode said data. A method according to one embodiment includes determining and comparing a CTR and an expected CTR to determine whether to encode the outgoing data. Any one of a plurality different coding techniques may be used including bus inversion.

A method for determining an error vector for a data word according to a Reed-Muller Code includes determining the syndrome of the error vector according to the Reed-Muller Code, expanding the syndrome with zeroes to 1 bit length less than the length of the Reed-Muller Code, determining a code word of a Simplex Code of 1 bit length less than the length of the Reed-Muller Code whose difference to the expanded syndrome has a weight below a first threshold or equal to or above a second threshold, expanding the difference between the determined code word and the expanded syndrome by a zero, and outputting the expanded difference as error vector if its weight is below the first threshold or outputting the inverted expanded difference as error vector if the weight of the expanded difference is equal to or above the second threshold.

A method for determining an error vector for a data word according to a Reed-Muller Code includes determining the syndrome of the error vector according to the Reed-Muller Code, expanding the syndrome with zeroes to 1 bit length less than the length of the Reed-Muller Code, determining a code word of a Simplex Code of 1 bit length less than the length of the Reed-Muller Code whose difference to the expanded syndrome has a weight below a first threshold or equal to or above a second threshold, expanding the difference between the determined code word and the expanded syndrome by a zero, and outputting the expanded difference as error vector if its weight is below the first threshold or outputting the inverted expanded difference as error vector if the weight of the expanded difference is equal to or above the second threshold.

A method for reading data from an SSD, comprising: retrieving data from a target row of memory cells using initial threshold voltages; decoding the data using a first hard decision decoding stage; estimating a bit error rate (BER) of a target row of memory cells based on a distribution of threshold voltages of cells in a memory block containing the target row when the first hard decision decoding stage fails; classifying the BER of the target row based on a first BER threshold (BER-TH1); and executing a first read flow comprising at least one hard decision decoding stage if the BER is less than the BER-TH1, and executing a second read flow similar to the first read flow if the BER is greater than or equal to the BER-TH1, the second read flow skipping a hard decision decoding stage of the first read flow.

A decoding method includes a threshold determining mechanism such that that a controller chip can simultaneously perform calculation of a quantity of check equations that are not met by a bit and a bit flipping process. In addition, an algorithm for calculating the quantity of check equations that are not met by each bit is optimized.

A decoding method includes a threshold determining mechanism such that that a controller chip can simultaneously perform calculation of a quantity of check equations that are not met by a bit and a bit flipping process. In addition, an algorithm for calculating the quantity of check equations that are not met by each bit is optimized.

Techniques for decoding a low-density parity check (LDPC) can include determining an asymmetric ratio of bit errors read as logic zero to bit errors read as logic one. The energy of each variable node of the LDPC codeword can be computed. For each variable node having an energy greater than a threshold energy, the variable node can be added to a collection of candidate bits for bit flipping. The asymmetric ratio can then be applied to flip bits in the collection of candidate bits to decode the LDPC codeword.

Disclosed are a controller, a system and a method for decoding LDPC codewords based on historical decoding information. In a decoding iteration, the value of flipping energy of a variable node in a codeword is computed based on information representing decoding of the codeword before the decoding iteration. A comparison result is obtained by comparing the value of flipping energy to a flipping energy threshold. And the variable node is flipped in response to the comparison result satisfying a criterion. A controller with a process configured to implement the BF decoding process, as well as a system with the controller.