Patent classifications
H03M13/611
Channel encoding method and apparatus
A channel encoding method and apparatus. The method includes: obtaining A to-be-encoded information bits; mapping the A to-be-encoded information bits and L CRC bits to a first bit sequence based on an interleaving sequence, where the L CRC bits are obtained based on the A to-be-encoded information bits and a CRC polynomial, the interleaving sequence is obtained from a prestored interleaving sequence table or is obtained based on a maximum-length interleaving sequence, A+L is less than or equal to Kmax, and Kmax is a length of the maximum-length interleaving sequence; and encoding the first bit sequence. In this way, not only an encoding delay can be reduced, but also decoding has an early stop capability, so that decoding can end in advance, thereby reducing a decoding delay.
ROBUST RETRANSMISSION TOPOLOGIES USING ERROR CORRECTION
Methods and systems for improving the robustness of wireless communications. The methods and systems provided transmit data packets over one or more isochronous stream and transmit one or more supplemental data packets over the same time intervals. The one or more supplemental data packets are used to recreate and/or enhance at least a portion of one or more data packets of the plurality of data packets that have already been sent. Alternatively, the one or more supplemental data packets are used to create and/or enhance at least a portion of one or more data packets of the plurality of data packets that will be received during the next isochronous intervals. The methods and system described herein allow for increased robustness by allowing for better retransmission with correctly received packets.
Conversion of Pauli errors to erasure errors in a photonic quantum computing system
A quantum computing system for converting Pauli errors of one or more qubits to erasure errors in a photonic quantum computing architecture. Two or more photonic qubits may be input to a quantum computing system, where at least one first qubit of the two or more qubits has experienced a Pauli error. A sequence of linear optical circuitry operations may be performed on the two or more qubits to generate two or more modified qubits, wherein the sequence of operations transforms one or more of the first qubits from a logical subspace of a Fock space to an erasure subspace of the Fock space. A cluster state for universal quantum computing may be generated from the two or more modified qubits using probabilistic entangling gates. A quantum computational algorithm may be performed using the quantum cluster state generated from the two or more modified qubits.
Method and apparatus for signal receiving and deinterleaving
A signal receiving method include: demodulating a signal received from a transmitting apparatus to generate values based on 1024-quadrature amplitude modulation (QAM); splitting the values into a plurality of groups; deinterleaving the plurality of groups based on a preset interleaving order; and decoding values of the deinterleaved plurality of groups based on a low density parity check (LDPC) code, a code rate of the LDPC code being 6/15 and a code length of the LDPC code being 64800, wherein the plurality of groups are deinterleaved based on a predetermined equation.
DETECTION CIRCUIT AND DETECTION METHOD, ELECTRONIC DEVICE, AND COMPUTER-READABLE STORAGE MEDIUM
The invention relates to a detection circuit, a detection method, an electronic device, and a computer-readable storage medium. The detection circuit includes: an error correction coding module configured to obtain data to be checked, and perform, based on an error correction coding logic, error correction coding on the data to be checked, to output target coded data; a data mask interface configured to receive comparison coded data, where the comparison coded data is associated with ideally coded data of the data to be checked; a comparison checking module configured to perform a checking comparison on the target coded data and the comparison coded data to output a checking comparison result; and a logic verification module configured to determine a coding verification result of the error correction coding module based on the checking comparison result. The comparison checking data verifies correctness of the error correction coding logic.
METHOD FOR GENERATING BURST ERROR CORRECTION CODE, DEVICE FOR GENERATING BURST ERROR CORRECTION CODE, AND RECORDING MEDIUM STORING INSTRUCTIONS TO PERFORM METHOD FOR GENERATING BURST ERROR CORRECTION CODE
There is provided a method for generating a burst error correction code. The method comprises: setting a mother code; defining a syndrome set corresponding to each burst error pattern for at least two burst error patterns to be corrected based on the mother code; shortening a column of a PCM (parity check matrix) of the mother code so that the defined syndrome sets are relatively prime; and designing an error correction code for the each burst error pattern based on an optimal generator polynomial maximizing a length of the shortened code within a range of a length of a parity bit of the mother code or a syndrome vector included in the syndrome set that is relatively prime.
Polar coding system and parallel computation method for polar coding system
The invention refers to the parallel calculation method for polarization coding (PCPE) for channel coding technique in 5th next generation mobile communication systems which includes to split N-bits input sequence into X parallel streams, each stream has Y bits; to multiply Y bits at each stream by the columns of the Kronecker matrix G.sub.Y, the results are displayed in rows according to the principle of bit elimination; and to multiply the matrix obtained with the columns of the Kronecker matrix G.sub.X according to the sample repeat and scalar multiplication. In addition, the invention also refers to the polarization coding system according to the Parallel Computation for Polarization Encoding (PCPE) for the channel coding technique in the 5th next generation mobile communication system.
Memory system using a quantum convolutional code
A memory system comprising a qubit array configured to store therein one or more entangled qubit states encoded using a quantum stabilizer code. The memory system further comprises a quantum-state-refresh module configured to refresh an entangled qubit state in the qubit array when a degradation error is detected therein. The quantum-state-refresh module is further configured to detect the degradation error by performing a redundant measurement of a set of syndrome values corresponding to the quantum stabilizer code. The redundant measurement is based on an error-correction code defined using the generator matrix of the quantum stabilizer code and a corresponding supplemental parity-check matrix. In an example embodiment, each of the generator and supplemental parity-check matrices has a respective inclined-stripe form.
METHOD OF PERFORMING A DISTRIBUTED TASK OVER A NETWORK
An aspect of the invention provides a method of performing a distributed task over a network comprising a plurality of nodes. The method comprises: a plurality of network nodes observing (300) data; applying a first linear code function to the data observed by at least one network node of the plurality of network nodes to obtain (302) at least one function output; applying errors (304) to the at least one function output; a query node selected from the network nodes performing (308) a mixing procedure to aggregate node observations to obtain a first set of aggregated values until a stopping criteria (306) is satisfied; applying (312) a second linear code function to the set of aggregated values to obtain a second set of aggregated values returned to their observed domain; and the query node outputting (314) the second set of aggregated values.
HAMMING WEIGHT CALCULATION METHOD BASED ON OPERATION APPARATUS
The present application discloses a Hamming weight calculation method performed by an operation apparatus. The operation apparatus includes a controller and a first calculator, wherein the controller sets an initial resistance state of the first memory to a low resistance state; determines a first gate voltage of the first transistor based on first bit data in a first binary sequence, and control an on-off state of the first transistor based on the first gate voltage; controls a target resistance state of the first memory based on the on-off state of the first transistor; and determines a Hamming weight of the first bit data based on a first output current on the source of the first transistor.