An apparatus for inserting an error correction code according to an embodiment includes an identifier configured to identify a plurality of critical sets included in a codeword generated using a polar code, based on the number of information bits and a total code length of the codeword, a divider configured to divide the codeword into a plurality of partitions, and an inserter configured to insert an error correction code into each of the divided partitions based on a distribution position of each of the plurality of critical sets.

An error rate measuring apparatus includes: an operation unit that sets a codeword length, an FEC symbol length, and an FEC symbol error threshold in accordance with a communication standard of a device under test W; error counting means for counting FEC symbol error detected at one FEC symbol interval and an uncorrectable codeword; a display unit that identifies and displays bit string data according to presence or absence of the FEC symbol error in FEC symbol length units based on a counting result; and display control means for performing display control by setting one zone of a display area of identification display as one FEC symbol length, matching a zone length of a horizontal axis of the display area with one codeword length, and performing line feed in codeword length units.

A polar code encoding method includes obtaining, by an encoding apparatus, to-be-encoded bits, a mother code length, and a first sequence. The first sequence includes sequence numbers of polarized subchannels. The sequence numbers of the polarized subchannels are arranged in the first sequence based on reliability of the polarized subchannels. The method also includes determining, based on the first sequence, polarized subchannels used to contain the to-be-encoded bits, and performing polarization encoding on the to-be-encoded bits to obtain an encoded bit sequence. The method further includes performing rate matching on the encoded sequence to obtain a rate-matched sequence. The method additionally includes outputting the rate-matched sequence.

A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.

Improved error correction systems and methods for wireless networks are described herein. A method can include generating a first cyclic redundancy code (CRC) for a payload of a data packet by executing cycles for sets of input bytes from the payload using a CRC algorithm so as to reduce a number of the cycles required to generate the first CRC when compared to generating the first CRC from individual bits of the payload, appending the first CRC to the payload of the data packet, and transmitting the data packet over a wireless link from a source to a sink.

A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.

The disclosed systems, structures, and methods are directed to encoding and decoding information for transmission across a communication channel. The encoding method includes: distributing the information bits between m parallel polar codes such that each of the m parallel polar codes includes a subset of the information bits; splitting the subset of information bits in each of the m parallel polar codes into a protected information section and a full rate information section; protecting information bits in the protected information section of each of the m parallel polar codes; arranging a plurality of frozen bits in each of the m parallel polar codes; and generating a polar encoded codeword for each of the m parallel polar codes.

A cyclo-stationary characteristic of a communications channel and/or storage media is determined. The cyclo-stationary characteristic has K-cycles, K > 1. Markov transition probabilities are determined that depend on a discrete phase ϕ=t mod K, wherein t is a discrete time value. An encoder to optimize the Markov transition probabilities for encoding data sent through the communications channel and/or stored on the storage media. The optimized Markov transition probabilities are used to decode the data from the communication channel and/or read from the storage media.

The present application relates to AC driven control systems that attains high level of functional integrity at one or more location. The present application discloses an AC driven control system that implements the technique of segregating domains of plurality of AC supply based functions using DC encoding thereby attaining high level of functional integrity of load devices that are being remotely operated.

An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.