Patent classifications
H03M13/611
Failure abatement approach for a failed storage unit
A method for execution by a vault management device of a storage network includes determining a failure impact level to vaults of the storage network based on a failed storage unit within the vaults, where the vaults include a first vault that is associated with a first set of storage units and a first decode threshold number, and a second vault that is associated with a second set of storage units and a second decode threshold number, and where the failure impact level is based on the number of non-failed storage units within each of the vaults. The method continues with determining a failure abatement approach based on the failure impact level. The method continues by with facilitating the failure abatement approach.
ON-DEMAND DECODING METHOD AND APPARATUS
This application discloses decoding methods, apparatuses, and computer-readable storage media, which may be applied to a plurality of scenarios such as a metropolitan area network, a backbone network, and data center interconnection. An example method includes: obtaining syndromes corresponding to a plurality of codewords; grouping the syndromes into groups; and sorting priorities of each group of syndromes; and selecting, based on a priority sorting result of each group of syndromes, a syndrome for decoding.
ERROR CORRECTION CODE (ECC) OPERATIONS IN MEMORY
Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include generating a codeword based on a number of low density parity check (LDPC) codewords failing a LDPC decoding operation and performing a BCH decoding operation on the codeword.
Processing-in-memory instruction set with homomorphic error correction
A method includes generating an ECC encoded output data by executing an ECC-Space operation using an ECC encoded first data from a memory as a first operand and an ECC encoded second data from the memory as a second operand. The ECC-Space operation is translated from a two operands operation that is operative to transform a first data and a second data into a third data. A result of encoding the first data is the ECC encoded first data and a result of encoding the second data is the ECC encoded second data if the first data and the second data are encoded with an ECC algorithm. The method also includes storing the ECC encoded output data to the memory. The ECC encoded output data is identical to a result of encoding the third data if the third data is encoded with the ECC algorithm.
USING STORLET IN ERASURE CODE OBJECT STORAGE ARCHITECTURE FOR IMAGE PROCESSING
Embodiments of the present invention provide methods, systems, and computer program products for using a storlet erasure code object storage architecture for image processing. In one embodiment, an object is received, the object being represented as erasure coded bits. A storage location associated with the erasure coded bits is identified. A virtual machine (VM) is invoked, where the VM is configured to compute a modification to the erasure coded bits and replace the original erasure coded bits with the modified erasure coded bits.
Efficient high/low energy zone solid state device data storage
Methods and apparatus associated with storing data in high or low energy zones are described. Example apparatus include a data storage system (DSS) that protects a message using an erasure code (EC). A location in the DSS may have an energy efficiency rating or a latency. Example apparatus include circuits that produce EC encoded data that has a likelihood of use, that select a location to store the EC encoded data in the DSS based on the energy efficiency rating, the latency, or the likelihood of use, that store the EC encoded data in the location, and that compute an order of retrieval for EC encoded data stored in the location. The order of retrieval may be based on the energy efficiency rating or the latency. The EC encoded data may also have a priority based on the number of erasures for which the EC corrects.
GEOMETRY-BASED COMPRESSION FOR QUANTUM COMPUTING DEVICES
A quantum computing device comprises a surface code lattice that includes/logical qubits, where/is a positive integer. The surface code lattice is partitioned into two or more regions based on lattice geometry. A compression engine is coupled to each logical qubit of the/logical qubits. Each compression engine is configured to compress syndrome data generated by the surface code lattice using a geometry-based compression scheme. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.
Method and device for decoding data stored in a DNA-based storage system
A method includes obtaining, for each type of nucleotide, a probability density function, the probability density functions being obtained from measurements of current drops produced during at least one passage of at least one sequence of reference nucleotides through a nanopore sequencer; obtaining measurements of current drops produced when the sequence of nucleotides to be decoded passes through the nanopore sequencer; calculating, for each measurement value considered and for each type of nucleotide of the B types of nucleotides, a piece of reliability information based on the probability density function obtained for the type of nucleotide considered; obtaining a decoded value identifying a type of nucleotide from the B types of DNA nucleotides, by applying a soft decoding algorithm with an error correction code to the current drop measurement and to the B pieces of reliability information obtained for the considered measurement value.
Systems and methods for using not perfectly polarized bit channels in parallel polar codes
The disclosed systems, structures, and methods are directed to encoding and decoding information for transmission across a communication channel. The encoding method includes: distributing the information bits between m parallel polar codes such that each of the m parallel polar codes includes a subset of the information bits; splitting the subset of information bits in each of the m parallel polar codes into a protected information section and a full rate information section; protecting information bits in the protected information section of each of the m parallel polar codes; arranging a plurality of frozen bits in each of the m parallel polar codes; and generating a polar encoded codeword for each of the m parallel polar codes.
Data processing device and data processing method
A code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 is interchanged with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK. When 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and a bit b0 is interchanged with a bit y1, a bit b1 is interchanged with a bit y0, and a bit b2 is interchanged with a bit y2.