A system and method for detecting an angle of arrival (AoA) of incident waves are disclosed. An array of wave sensors each transduce incident waves into an electrical signal, which is then provided an additional phase shift that varies between sensors. Electrical signals from adjacent wave sensors, having different phase shifts, are coupled via a phase detector to classify the incident waves into zero and one AoA regions for that sensor pair. The outputs from many such phase detectors are combined to divide the space facing the array into many subregions, each subregion being associated with a unique codeword. Incident waves cause detection of codewords, that are decoded according to error detection and correction techniques, such as selecting, from a list, the codeword having a minimum Hamming distance to a received codeword. The decoder then outputs data indicating an AoA subregion associated with the decoded codeword.

Systems and methods are disclosed for error correction with multiple log likelihood ratio (LLR) lookup tables (LUTs) for a single read, which allows for adaptation to asymmetry in the number of 0 or 1 bit errors without re-read operations. In certain embodiments, an apparatus may comprise a circuit configured to receive a sequence of bit value estimates for data read from a solid state memory during a single read operation, generate a first sequence of LLR values by applying the sequence of bit value estimates to a first LUT, and perform a decoding operation on the first sequence of LLR values. When the first sequence of LLR values fails to decode, the circuit may be configured to generate a second sequence of LLR values by applying the bit value estimates to a second LUT, and perform the decoding operation on the second sequence of LLR values to generate decoded data.

An example method for determining likelihood of erroneous data bits stored in memory cells may include sensing a first plurality of memory cells based on a first sense thresholds. Responsive to sensing the first plurality of cells, a first set of probabilistic information may be associated with the first plurality of memory cells. A second plurality of memory cells may be sensed based on a second sense threshold. Responsive to sensing the second plurality of memory cells, a second set of probabilistic information may be associated with the second plurality of memory cells. An error correction operation may be performed on the first and second pluralities of memory cells based, at least in part, on the first and second values.

Disclosed herein are memory devices, systems, and methods of encoding and decoding data. In one aspect, an encoded data chunk is received and segmented into data segments with similar features. Each segment can be decoded based on its features. Data can also be rearranged and partitioned so as to minimize an entropy score that is based on the size and entropy of the data partitions. The approach is capable of enhancing performance, reducing decoding latency, and reducing power consumption.

Wireless communications systems and methods are introduced. A wireless communication device may arrange a first encoded information block including a first sub-block having a first bit location and a second sub-block having a second bit location. The second bit location is after the first bit location. The wireless communication device may also position the first location earlier in a decoding order of a receiving second wireless communication than the second bit location. The wireless communication device may transmit the first and second sub-blocks as an encoded information block to the second wireless communication device.

Disclosed herein are memory devices, systems, and methods of encoding and decoding data. In one aspect, an encoded data chunk is received and segmented into data segments with similar features. Each segment can be decoded based on its features. Data can also be rearranged and partitioned so as to minimize an entropy score that is based on the size and entropy of the data partitions. The approach is capable of enhancing performance, reducing decoding latency, and reducing power consumption.

An apparatus and method for optimizing a physical layer parameter is provided. According to one embodiment, an apparatus includes a first neural network configured to receive a transmission environment and a block error rate (BLER) and generate a value of a physical layer parameter; a second neural network configured to receive the transmission environment the BLER and generate a signal to noise ratio (SNR) value; and a processor connected to the first neural network and the second neural network and configured to receive the transmission environment, the generated physical layer parameter, and the generated SNR, and to generate the BLER.

An optical transmission apparatus (100) generates a second bit sequence B by encoding a first bit sequence b having forward error correction coding performed on a transmission bit sequence, maps the second bit sequence to a transmission symbol signal, and transmits an optical modulated signal generated by modulating an optical carrier wave into the transmission symbol signal. A symbol output unit (2020) generates a received symbol signal by demodulating an optical modulated signal received by an optical reception apparatus (2000). A first computation unit (2040) computes LLR(Bi) which is a log-likelihood ratio (LLR) of each bit Bi of the second bit sequence, using the received symbol signal. A second computation unit (2060) computes a log-likelihood ratio LLR(bi) of each bit bi of the first bit sequence from the LLR(Bi). A correspondence relationship between each bit of the first bit sequence and each bit of the second bit sequence is used in this computation. A decoding unit (2080) decodes the transmission bit sequence using the LLR(bi).

Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.