Embodiments described herein provide a system for dynamically selecting a pre-processing scheme for an LDPC decoder. The system includes a receiver configured to detect transmission of a first data packet and receive a first set of data bits corresponding to a first portion of the first data packet. The system further includes a histogram generator configured to calculate log-likelihood ratios for each data bit from the first set of data bits, and generate a histogram based on the calculated log-likelihood ratios. The receiver is configured to continue receiving a second set of data bits corresponding to a second portion of the first data packet. The system further includes a selector configured to activate or inactivate a log-likelihood ratio pre-processing scheme on the received second set of data bits based on characteristics of the histogram.

Systems, methods, and computer readable media are described for effectively using dither techniques upon signals having a predicted quantization error that varies across the range of the signal. In some embodiments, predicted error is used to shape a precision input signal so that the newly-shaped signal yields a uniform or relatively uniform predicted quantization error. A dither is applied to the re-shaped signal, and the shaping is reversed, after which the signal may be slope limited and/or quantized, taking full and efficient advantage of the dithering technique.

A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.

There is provided a method of extracting a noise defect from defect data. The method comprises obtaining the defect data including data on a plurality of defects, determining one of a plurality of abnormal value calculators for calculating abnormal values using each of a variety of predetermined calculation methods and calculating an abnormal value for each of the plurality of defects using one of the plurality of abnormal value calculator, generating a frequency histogram for each of the plurality of defects using the abnormal value, calculating similarity between the plurality of defects using the frequency histogram for each of the plurality of defects, and extracting the noise defect from the plurality of defects based on the similarity

Methods and apparatuses for determining likelihood of erroneous data bits stored in a plurality of memory cells. A sense circuit to perform a coarse sense operation to detect first memory cells of the plurality of memory cells that stored charge sufficiently above a transition voltage threshold where the first memory cells are unlikely to be erroneous. The sense circuit further performs a fine sense operation to sense second memory cells of the plurality of memory cells having stored charge near the transition voltage between adjacent logic states. The first memory cells remain unsensed during the fine sense operation. The second memory cells detected during the fine sense operation may have an increased likelihood of being erroneous. Responsive to a number of sensed second memory cells near the transition voltage exceeding a threshold, additional sensing operations are performed by the sense circuit.

Read threshold voltage tracking techniques are provided for multiple dependent read threshold voltages using syndrome weights. One method comprises reading codewords of multiple pages using different first read threshold voltages and a default second read threshold voltage; decoding read values for the multiple pages for the different first read threshold voltages and the default second read threshold voltage; aggregating a syndrome weight for each failed decoding attempt for the different first read threshold voltages; identifying a selected first read threshold voltage using a corresponding syndrome weight; reading codewords of the multiple pages using the selected first read threshold voltage and different second read threshold voltages; decoding read values for the selected first read threshold voltage and the different second read threshold voltages; aggregating the syndrome weight for the different second read threshold voltages; and identifying a selected second read threshold voltage using a corresponding syndrome weight.

Methods and apparatus are provided for read retry operations that estimate written data based on syndrome weights. One method comprises reading a codeword from a memory multiple times using multiple read reference voltages; obtaining a syndrome weight for each of the readings of the codeword; identifying a given reading of the codeword having a substantially minimum syndrome weight; and estimating a written value of the codeword based on the given reading. Two cell voltage probability distributions of cell voltages are optionally calculated for each possible cell state of the memory, based on the estimated written value and plurality of readings of the codeword. The cell voltage probability distributions are used to (i) dynamically select log likelihood ratio values for a failing page, (ii) determine a read reference voltage that gives a desired log likelihood ratio value, or (iii) dynamically select log likelihood ratio values for the page populations associated with the distributions.

A storage system includes: a control processor unit, configured to: initiate a read of a raw data page, having correctable errors, calculate a raw bit error rate (RBER) (EQ1) by correcting the correctable errors to become corrected data and comparing raw data with the corrected data, and calculate a correction model characterization based on the RBER (EQ1); and a non-volatile storage array, coupled to the control processor unit, configured to store a processed data page in a physical block with the raw data page; and wherein the control processor unit is further configured to apply the correction model characterization to the raw data page in the physical block.

A wireless communication device suppresses increase in computation scale when applying maximum likelihood detection to a multi-level modulation scheme. Units calculate a likelihood, bit log-likelihood ratio, and mutual information content for the separation result of a received signal on the basis of the signal point of a reference selected from among a plurality of signal points that a transmitted signal can assume. A transmission candidate point selection unit selects signal points in a number that corresponds to the mutual information content as transmission candidate points from among the plurality of signal points in ascending order of distance to 0 and distance to 1 for each modulation bit that constitutes the signal point of the reference. A reception candidate point that is a candidate for the received signal is calculated. An external LLR calculation unit calculates the bit log-likelihood ratio by an MLD method.

An apparatus for generating a frozen set associated with a polar code of length N and dimension K comprises a processing unit configured to take in input the polar code length N, the dimension K, and a profile of a structure of a block lower triangular affine (BLTA) group. The BLTA group structure is associated with an affine transformation matrix of size n?n and the profile is an ordered set of a plurality of values corresponding to block sizes of blocks. The blocks are sub-matrices of the affine transformation matrix with all the diagonals of blocks in the same order as the ordered block sizes, forming the diagonal of the affine transformation matrix, each of the block sizes is such that n is equal to the sum of block sizes and n is equal to log.sub.2(N). The processing unit generates the frozen set.