Patent classifications
H03M13/618
Method and apparatus for low density parity check channel coding in wireless communication system
Embodiments of this application disclose provides a low density parity check (LDPC) channel encoding method for use in a wireless communications system. A communication device encodes an input bit sequence by using a LDPC matrix, to obtain an encoded bit sequence for transmission. The LDPC matrix is obtained based on a lifting factor Z and a base matrix. Embodiments of the application provide eight particular designs of the base matrix. The encoding method provided in the embodiments of the application can be used in various communications systems including the fifth generation (5G) telecommunication systems, and can support various encoding requirements for information bit sequences with different code lengths.
METHOD AND APPARATUS FOR SHORTENING AND PUNCTURING NON-BINARY CODE
The present disclosure relates to a pre-5.sup.th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The present invention relates to a method and a device for efficiently shortening and puncturing a non-binary LDPC code, the method for a transmitter shortening and puncturing a non-binary code being capable of supporting various modulation methods by using a single non-binary code, and the method comprising the steps of: shortening, on the basis of a modulation method, at least one information bit in at least one information symbol constituting the non-binary code; encoding the at least one information symbol having a shortened information bit; and puncturing, on the basis of the modulation method, at least one parity code in at least one parity symbol obtained through the encoding step.
ERROR CORRECTION CODE (ECC) OPERATIONS IN MEMORY
The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.
Additional Bit Freezing For Polar Coding
Examples pertaining to additional bit freezing for polar coding are described. An apparatus performs polar coding to encode a plurality of input subblocks of information bits, frozen bits and optional cyclic redundancy check (CRC) bits to generate a plurality of subblocks of coded bits. The apparatus then transmits at least some of the subblocks of coded bits. In performing the polar coding, the apparatus additionally freezes one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits which decreases polarization gain due to puncturing.
Method and apparatus for LDPC transmission over a channel bonded link
A particular overall architecture for transmission over a bonded channel system consisting of two interconnected MoCA (Multimedia over Coax Alliance) 2.0 SoCs (Systems on a Chip) and a method and apparatus for the case of a “bonded” channel network. With a bonded channel network, the data is divided into two segments, the first of which is transported over a primary channel and the second of which is transported over a secondary channel.
Interleaving method and apparatus
An interleaving method and apparatus are provided, to reduce complexity of implementation processes of polar code interleaving and rate matching. The method includes: obtaining encoded bits after polar code encoding, and sorting the encoded bits based on a priority order of performing a rate matching operation, to obtain a first bit sequence. The first bit sequence includes j subsequences, and j is a positive integer. The method further includes writing the first bit sequence into an interleaver of i rows and j columns. Bits in a column in the interleaver include one of the j subsequences; and reading out bits from the interleaver column by column, until M bits are read. At least two adjacent columns have opposite readout directions, and M is a target code length.
ERROR RATE REDUCTION
The present disclosure includes apparatuses and methods for error rate reduction. One example method comprises adding an amount of error rate reduction (ERR) data to an amount of received user data, and writing the amount of user data along with the amount of ERR data to a memory.
SLICED POLAR CODES
An apparatus for polar coding includes an encoder circuit that implements a transformation C=u.sub.1.sup.N-sB.sub.N-s{tilde over (M)}.sub.n, wherein u.sub.1.sup.N-s, B.sub.N-s, {tilde over (M)}.sub.n, and C are defined over a Galois field GF(2.sup.k), k>1, wherein N=2.sup.n, s<N, u.sub.1.sup.N-s=(u.sub.1, . . . , u.sub.N-s) is an input vector of N−s symbols over GF(2.sup.k), B.sub.N-s is a permutation matrix, {tilde over (M)}.sub.n=((N−s) rows of M.sub.n=), the matrix M.sub.1 is a pre-defined matrix of size q×q, 2<q and N=q.sup.n, and C is a codeword vector of N−s symbols, and wherein a decoding complexity of C is proportional to a number of symbols in C; and a transmitter circuit that transmits codeword C over a transmission channel.
POLAR CODING METHOD, APPARATUS, AND DEVICE
Embodiments of this application disclose a polar coding method, apparatus, and device, so as to reduce storage overheads of a system. A sequence for polar coding is obtained based on a length M of a target polar code, wherein the sequence comprises L sequence numbers, ordering of the L sequence numbers in the sequence is the same as ordering of the L sequence numbers in a maximum mother code sequence, wherein the maximum mother code sequence is obtained by sorting N sequence numbers of N polarized channels in ascending order or descending order of reliability metrics, wherein L and N are integer power of 2, M is smaller than or equal to L, L is smaller than or equal to N.
Decoding Method and Device for Turbo product codes, decoder and computer storage medium
A decoding method and device for Turbo product codes, a decoding device, a decoder and a computer storage medium are provided. The method includes: a received codeword of a Turbo product code is acquired, and iterative decoding is performed on the received codeword for a set first iterative decoding times (S101); a decoding result of iterative decoding performed for the first iteration times is judged according to a first decoding rule to obtain a decoding identifier representing the decoding result (S102); and error correction processing is performed on the Turbo product code on which iterative decoding is performed for the first iteration times according to the decoding identifier (S103).