A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

The invention provides a signal processing device, including: an extraction section that extracts, from an input digital signal, a decoding target signal at an extraction timing that has been determined as a timing for extracting the decoding target signal; a decoding section that decodes the decoding target signal by estimating, by a maximum likelihood decoding, a candidate for a decoding result of the decoding target signal extracted by the extraction section and detecting a maximum likelihood decoding result; and an adjustment section that adjusts the extraction timing using a likelihood of the candidate for the decoding result estimated by the decoding section.

A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: programming a first memory cell in a rewritable non-volatile memory module; reading the first memory cell based on a first hard-decision voltage level to obtain first hard-bit information and perform a hard-decoding process accordingly; if the hard-decoding process fails and the first memory cell belongs to a first type memory cell, reading the first memory cell based on a second hard-decision voltage level to obtain second hard-bit information and perform another hard-decoding process accordingly; if the hard-decoding process fails and the first memory cell belongs to a second type memory cell, reading the first memory cell based on multiple second soft-decision voltage level to obtain soft-bit information and perform soft-decoding process accordingly. Therefore, a balance can be maintained between a decoding speed and a decoding success rate.

Communication systems are described that use geometrically shaped constellations that have increased capacity compared to conventional constellations operating within a similar SNR band. In several embodiments, the geometrically shaped is optimized based upon a capacity measure such as parallel decoding capacity or joint capacity. In many embodiments, a capacity optimized geometrically shaped constellation can be used to replace a conventional constellation as part of a firmware upgrade to transmitters and receivers within a communication system. In a number of embodiments, the geometrically shaped constellation is optimized for an Additive White Gaussian Noise channel or a fading channel.

A syndrome weight of failed decoding attempts is used to select parameters for future read retry operations. The following exemplary steps are performed until a decoding success or a predefined limited number of readings is reached: (i) reading a codeword using different read threshold voltages; (ii) mapping the readings to a corresponding likelihood value using a likelihood value assignment; and (iii) recording a syndrome weight for failed decoding attempts of the readings using the different read threshold voltages. Once the predefined limit is reached, the following exemplary steps are performed: (i) mapping the readings to a corresponding likelihood value using different likelihood value assignments, and (ii) recording a syndrome weight for failed decoding attempts of the readings using the different likelihood value assignments; and using a given read threshold voltage and/or a likelihood value assignment associated with a substantially minimum syndrome weight as an initial read threshold voltage and/or a higher priority read threshold voltage for subsequent read retry operations.

Described is a method which comprises performing a first read from a portion of a non-volatile memory, the first read to provide a first codeword; decoding the first codeword; determining whether the decoding operation failed; performing a second read from the portion of the non-volatile memory when it is determined that the decoding operation failed, the second read to provide a second codeword; and decoding the second codeword with an errors-and-erasures decoding process.

Reduction in deterioration of a memory cell in a non-volatile memory is achieved. A memory controller is configured to include a time measuring unit, an elapsed time determination unit, and a read unit. The time measuring unit measures time elapsed from predetermined timing on an address where data written. The elapsed time determination unit determines whether the elapsed time exceeds a fixed amount of time upon receiving an instruction to read out the data from the address. The read control unit causes reading-out of the data from the address to pause in a case where the elapsed time is determined not to exceed the fixed amount of time.

A data storage device may include a memory and a controller that includes an error correction coding (ECC) decoder configured to operate in a plurality of decoding modes. The controller also includes a bit error rate estimator configured to determine, based on data received from the memory, bit error rate estimates for ECC codewords from the memory. The controller also includes a data path management unit configured to reorder the codewords based on the bit error rate estimates and to provide the reordered codewords to the ECC decoder.

In an illustrative example, an apparatus includes a controller and a memory that is configured to store a codeword of a convolutional low-density parity-check (CLDPC) code. The codeword has a first size and includes multiple portions that are independently decodable and that have a second size. The controller includes a CLDPC encoder configured to encode the codeword and a CLDPC decoder configured to decode the codeword or a portion of the codeword.

A hard-decision (HD) forward error correcting (FEC) coded signal is decoded by a decoder to produce decoded bits using marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal. The marked reliable and unreliable bits are computed by calculation and marking blocks based on an absolute value of log-likelihood ratios of the HD-FEC coded signal. The HD-FEC coded signal may be, for example, a staircase code coded signal or a product code coded signal.