A method is provided for determining log-likelihood ratio (LLR) for soft decoding based on information obtained from hard decoding, in a storage system configured to perform hard decoding and soft decoding of low-density parity-check (LDPC) codewords. The method includes performing hard decoding of codewords in a page, the hard decoding including a first hard read and one or more re-reads using predetermined hard read threshold voltages, and grouping memory cells in the page into a plurality of bins based on the read threshold voltages for the first hard read and the one or more re-reads. The method also includes computing parity checksum and one's count for memory cells in each bin, and determining LLR for each bin of memory cells based on read data, checksums, and one's count for each bin.

Systems and methods are provided for performing error recovery using LLRs generated from multi-read operations. A method may comprise selecting a set of decoding factors for a multi-read operation to read a non-volatile storage device multiple times. The set of decoding factors may include a total number of reads, an aggregation mode for aggregating read results of multiple reads, and whether the read results include soft data. The method may further comprise issuing a command to the non-volatile storage device to read user data according to the set of decoding factors, generating a plurality of Log-Likelihood Ratio (LLR) values using a mapping engine from a pre-selected set of LLR value magnitudes based on the set of decoding factors, obtaining an aggregated read result in accordance with the aggregation mode and obtaining an LLR value from the plurality of LLR values using the aggregated read result as an index.

The controller that controls a memory device includes: a processor suitable for controlling the memory device to perform a first soft read operation by using first soft read voltages; and an error correction code (ECC) codec suitable for performing a first soft decision decoding operation based on first soft read data obtained through the first soft read operation, wherein the processor controls the memory device to perform a second soft read operation with an additional read voltage, of second soft read voltages, that is different than any of the first soft read voltages and which is determined based on the first soft read data, according to whether the first soft decision decoding operation failed, and wherein the ECC codec performs a second soft decision decoding operation based on the first soft read data and second soft read data obtained through the second soft read operation.

Exemplary methods, apparatuses, and systems include receiving a request for a segment of data. The requested segment data is one of a plurality of segments of data in a stripe of data. A failure to decode the requested segment is detected. Each of the plurality of segments in the stripe other than the requested segment are read. Reading each segment includes reading raw encoded data and attempting to decode the raw encoded data, the result of reading each segment including decoded data when decoding is successful and the raw encoded data when decoding fails. A combined result of each read is generated. The combining includes combining decoded data for segments that were successfully decoded and the raw encoded data for segments for which decoding failed. A statistical model for the requested segment is updated using the combined result. The requested segment is decoded using the updated statistical model.

Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

Read data associated with Flash storage is received. One of a plurality of LLR mapping tables is selected and a set of one or more LLR values is generated using the read data and the selected LLR mapping table, where each LLR value in the set of LLR values has a same finite precision as a finite-precision low-density parity-check (LDPC) decoder. Error-corrected read data is generated using the set of LLR values, where the finite-precision LDPC decoder has the same finite precision as the set of LLR values. The error-corrected read data is output.

Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.

According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

A decoding system and method of a non-volatile memory are provided in which information regarding a characteristic of a non-volatile memory is used to determine an initial log-likelihood-ratio (LLR) table from among a number of LLR tables. The decoding is then performed using the determined initial LLR table.

The system and method described provide correction of modulation symbol errors which may occur during audio pairing of computing devices. The transmission between the computing devices comprises a six modulation symbol (24 bit) token containing transaction information and a two check symbol (8 bit) cyclic redundancy check (“CRC”). Error probabilities of symbols are be used to identify probable symbol error locations and the number of errors contained in the received transmission during the symbol decoding process. If there is a single modulation symbol error, the 16 possible combinations of bit values are cycled through until one combination passes the CRC check. If there are two modulation symbol errors, the 256 possible combinations of bit values are cycled through until two combinations pass the CRC check.