H03M13/6331

FAST-CONVERGING SOFT BIT-FLIPPING DECODER FOR LOW-DENSITY PARITY-CHECK CODES
20210143837 · 2021-05-13 ·

Disclosed are devices, systems and methods improving the convergence of a soft bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated based on a parity check matrix of an LDPC code and provided to a communication channel prior to reception by the soft bit-flipping decoder, generating, based on the noisy codeword, one or more messages for passing between a plurality of variable nodes and a plurality of check nodes of the soft bit-flipping decoder, generating a reliability metric for each of the one or more messages, storing the reliability metric only for messages comprising magnitudes that are less than or equal to a predetermined threshold value; and performing, based on the one or more messages and the associated reliability metric for at least one of the one more messages, a single decoding iteration of the soft bit-flipping decoder.

OPTIMIZATION OF ALL SOFTWARE MODEM USING FLEXIBLE CONFIGURATION PARAMETERS FOR HIGH-PERFORMANCE COMPUTING (HPC)

A method to provide flexibility on the configuration and operation of the modulator, demodulator, and modem, where purpose-built (legacy) devices are not traditionally capable of exposing a level of control and flexibly for a user or an autonomous program for optimizing performance. Providing user or programmatic control of algorithms is traditionally not possible for purpose-built modems. Parameters such as the number of decoder iterations that are performed on Forward Error Correction (FEC), Interference Mitigation algorithm, or dynamic adjustment loop bandwidth to combat phase noise can be adjusted autonomously to optimize receiver performance. The all software modem, supported by a High-Performance Computing (HPC) architecture, removes the limitation due to the flexibility of programming resources and available performance. Unlike most purpose-built hardware, the HPC allows processing resources to dynamically be reallocated, so that as additional performance is desired, the resources may be increased and decreased as required.

Signal transmission method and system
10958488 · 2021-03-23 · ·

This application provides a signal transmission method and system, and relates to the field of communications technologies. The system includes an equalization module, a first decoder, and a feedback module. The equalization module includes at least two multi-symbol detectors. The feedback module is connected to the first decoder and the at least two multi-symbol detectors. The equalization module performs equalization processing on convolutional data flows to obtain an equalized data flow. In this process, each multi-symbol detector performs multi-symbol detection processing on a convolutional data flow input into the multi-symbol detector. The first decoder decodes the equalized data flow to obtain a decoded data flow. The feedback module feeds back a feedback data flow to the at least two multi-symbol detectors. The equalization module performs equalization processing on the convolutional data flows based on the feedback data flow.

DEEP NEURAL NETWORK A POSTERIORI PROBABILITY DETECTORS AND MEDIA NOISE PREDICTORS FOR ONE-AND TWO-DIMENSIONAL MAGNETIC RECORDING

A deep neural network (DNN) media noise predictor configured for one-dimensional-magnetic (1DMR) recording or two-dimensional-magnetic (TDMR) is introduced. Such architectures are often combined with a trellis-based intersymbol interference (ISI) detection component in a turbo architecture to avoid the state explosion problem by separating the inter-symbol interference (ISI) detection and media noise estimation into two separate detectors and uses the turbo-principle to exchange information between them so as to address the modeling problem by way of training a DNN-based media noise estimators. Thus, beneficial aspects include a reduced bit-error rate (BER), an increased areal density, and a reduction in computational complexity and computational time.

DECODING DEVICE AND DECODING METHOD
20200366319 · 2020-11-19 ·

Deterioration of convergence performance or operational stability due to an increase in constraint length is suppressed when coefficients are updated, so that decoding performance is improved. A decoding device according to the present technology includes an adaptive equalization unit that performs adaptive equalization, an adaptive maximum likelihood decoding unit that causes an identification point of maximum likelihood decoding to adaptively follow a characteristic of an input signal, a target waveform generation unit that, by convoluting a partial response coefficient into a decoded value, generates an equalization target waveform of the adaptive equalization which is performed by the adaptive equalization unit, an error signal generation unit that generates, as an equalization error signal, an error signal between the equalization target waveform and an equalized signal, and a coefficient updating unit that, through least-square-method computation for minimizing a correlation between the decoded value and the equalization error signal, updates the partial response coefficient which is used by the target waveform generation unit to generate the equalization target waveform.

BANDWIDTH CONSTRAINED COMMUNICATION SYSTEMS WITH OPTIMIZED LOW-DENSITY PARITY-CHECK CODES

In some embodiments, a bandwidth constrained equalized transport (BCET) communication system comprises a transmitter that transmits a signal, a communication channel that transports the signal, and a receiver that receives the signal. The transmitter can comprise a pulse-shaping filter that intentionally introduces memory into the signal, and an error control code encoder that is a low-density parity-check (LDPC) error control code encoder. The error control encoder comprises code that is optimized based on the intentionally introduced memory into the signal, a code rate, a signal-to-noise ratio, and an equalizer structure in the receiver. In some embodiments, the communication system is bandwidth constrained, and the transmitted signal comprises an information rate that is higher than for an equivalent system without intentional introduction of the memory at the transmitter.

Receiver for wireless communication networks

An iterative receiver receives a signal including useful and interfering signal components, and detects information carried thereon. The receiver includes at least one estimating unit receiving the signal and providing an estimate of each signal component, and at least two decoding and regenerating units, at each iteration, each decoding and regenerating unit decoding a respective one among the estimates and for regenerating the respective decoded estimate into a respective regenerated estimate. At each receiver iteration, the at least one estimating unit provides estimates based on regenerated estimates provided at a previous iteration. The receiver further includes a control unit determines activation or deactivation of each decoding and regenerating unit at each process step of a detection process dedicated to detection of the signal, and determines, for each process step, a respective number of allowed iterations for each decoding and regenerating unit whose activation has been determined for that process step.

Bandwidth constrained communication systems with optimized low-density parity-check codes

In some embodiments, a bandwidth constrained equalized transport (BCET) communication system comprises a transmitter that transmits a signal, a communication channel that transports the signal, and a receiver that receives the signal. The transmitter can comprise a pulse-shaping filter that intentionally introduces memory into the signal, and an error control code encoder that is a low-density parity-check (LDPC) error control code encoder. The error control encoder comprises code that is optimized based on the intentionally introduced memory into the signal, a code rate, a signal-to-noise ratio, and an equalizer structure in the receiver. In some embodiments, the communication system is bandwidth constrained, and the transmitted signal comprises an information rate that is higher than for an equivalent system without intentional introduction of the memory at the transmitter.

MAXIMUM LIKELIHOOD ERROR DETECTION FOR DECISION FEEDBACK EQUALIZERS WITH PAM MODULATION

The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.

RECEIVER FOR WIRELESS COMMUNICATION NETWORKS

An iterative receiver receives a signal including useful and interfering signal components, and detects information carried thereon. The receiver includes at least one estimating unit receiving the signal and providing an estimate of each signal component, and at least two decoding and regenerating units, at each iteration, each decoding and regenerating unit decoding a respective one among the estimates and for regenerating the respective decoded estimate into a respective regenerated estimate. At each receiver iteration, the at least one estimating unit provides estimates based on regenerated estimates provided at a previous iteration. The receiver further includes a control unit determines activation or deactivation of each decoding and regenerating unit at each process step of a detection process dedicated to detection of the signal, and determines, for each process step, a respective number of allowed iterations for each decoding and regenerating unit whose activation has been determined for that process step.