Disclosed are a data decoding method and apparatus, and a computer storage medium. The data decoding method includes: after Polar code data to be decoded is acquired, transmitting the Polar code data to be decoded to at least two pre-configured independent U value calculation modules, the U value calculation modules being configured to calculate a U value required at a next iteration of a G node; controlling the at least two independent U value calculation modules to process the Polar code data to be decoded to obtain at least two sets of new decode data; and, processing the at least two sets of new decode data to obtain new Polar code data to be decoded.

The present disclosure a method of operating user equipment (UE) in a wireless communication system, the method comprising: identifying layer information that is applied to a neural polar code; generating, based on the identified layer information, transmission data by encoding data that is input into the neural polar code; and transmitting the transmission data to a base station, wherein, based on polar code transformation, the neural polar code generates the transmission data by performing encoding, based on the polar code transformation, from an initial layer of the data to a first layer according to the identified layer information and by performing encoding through a neural network-based autoencoder after the first layer until the transmission data is generated.

A variable width barrel shifter. The variable width barrel shifter includes a first barrel shifter configured to receive a data vector of width M as input. The variable width barrel shifter further includes a second barrel shifter configured to receive the data vector of width M as input. The variable width barrel shifter includes an element-wise multiplexer coupled to the first and second barrel shifters. The element-wise multiplexer is configured to provide a shifted output of the data vector of width M by including a first portion of output from the second barrel shifter and a second portion of output from the first barrel shifter.

The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a higher data transfer rate beyond a 4th generation (4G) communication system such as long term evolution (LTE). The present disclosure relates to encoding and decoding using a polar code in a wireless communication system. A method for operation of a first device in a wireless communication system may comprise the steps of: among sub-blocks including at least one node, identifying at least one inactive sub-block to deactivate the node operation in the sub-blocks; encoding data by using a construction matrix determined on the basis of the at least one inactive sub-block; and transmitting the encoded data to a second device.

Techniques related to improving power consumption of an LDPC decoder are described. In an example, the LDPC decoder uses a message passing algorithm between variable nodes and check nodes. A check node processing unit that generates check node to variable node messages implements a plurality of check node processing mode. Operation in each mode consumes a certain amount of power while providing a certain accuracy. Depending on a reliability of a variable node to check node message received by the check node processing unit, an appropriate check node processing mode is selected and used to generate a corresponding check node to variable node message. The reliability can be estimated for a set of variable node to check node messages based on, for instance, syndrome-related parameters.

A decoding device that includes a decoding determination unit to determine a procedure of recovering and decoding missing packets in consideration of a packet missing pattern in data including a set of media packets and redundant packets generated by a two-dimensional XOR-based FEC encoding method. Further, a decoding unit executes the recovery of the missing packets according to the procedure determined by the decoding determination unit.

Various implementations are directed to systems and methods for maintaining integrity and reliability of data in an SSD device using error correction coding. According to certain aspects, for frames of data having an ECC code with two or more sub-codes, while one sub-decoder is not in use it could be used to start a decode of another frame. By “interleaving” and alternating the frames between sub-decoders, two or more frames can be decoded simultaneously in an efficient manner. This can clearly be extended to more sub-codes (i.e. dimensions greater than two).

This invention presents a method and the corresponding hardware apparatus for decoding LDPC codes using a vertical layered (VL) iterative message passing algorithm. The invention operates on quasi-cyclic LDPC (QC-LDPC) codes, for which the non-zero circulant permutation matrices (CPMs) are placed at specific locations in the parity-check matrix of the codes, forming concentrated clusters of CPMs. The purpose of the invention is to take advantage of the organization of CPMs in clusters in order to derive a specific hardware architecture, consuming less power than the classical VL decoders. This is achieved by minimizing the number of read and write accesses to the main memories of the design.

A Viterbi Equalizer having a limited number of stages is disclosed. In some embodiments, the Viterbi Equalizer may have only four stages. The Viterbi Equalizer produces soft decisions, which comprise a final decision and reliability information related to that final decision. The Viterbi Equalizer is able to provide reliability information even if all paths do not converge on the final decision at the last stage. The reliability information is calculated based on if and when the paths in the trellis converge on a final decision. This reliability information can be used downstream, such as by another Viterbi Algorithm block to perform forward error correction. The use of soft decision provides gains of up to several dB in performance. Additionally, the Viterbi Equalizer is low cost and readily implemented in hardware or software.

A method and device for energy-efficient decoders. The decoder device can include a plurality of decoder modules configured to process an input data signal having a plurality of forward error correction (FEC) codewords. This plurality of decoder modules can include at least a first decoder followed by a second decoder. The first decoder can be low-power to first eliminate most of the errors of the codewords and the second decoder can be high-performance to correct the remaining errors. Alternatively, the first decoder can be high-performance to correct the codewords until the low-power decoder can correct the remaining errors. A classifier module can be included to determine portions of the codewords to be directed to any one of the plurality of decoder modules. These implementations can be extended to use additional decoders with different decoding algorithms and optimized to maximize decoder performance given a maximum power constraint.