[Object] To provide a communication control apparatus, a radio communication apparatus, a communication control method, a radio communication method, and a program that are capable of contributing to improving a radio communication technology related to IDMA. [Solution] Provided is a communication control apparatus including: a communication unit configured to communicate with a radio communication apparatus of a radio communication system using interleave division multiple access (IDMA); and a control unit configured to allocate an interleaver type of an interleaver to be used for IDMA by the radio communication apparatus.

Systems and methods for performing open-loop quantum error mitigation using quantum measurement emulations are provided. The open-loop quantum error mitigation methods do not require the performance of state readouts or state tomography, reducing hardware requirements and increasing overall computation speed. To perform a quantum measurement emulation, an error mitigation apparatus is configured to stochastically apply a quantum gate to a qubit or set of qubits during a quantum computational process. The stochastic application of the quantum gate projects the quantum state of the affected qubits onto an axis, reducing a trace distance between the quantum state and a desired quantum state.

According to one embodiment, a decoding device comprises a converter configured to convert read data to first likelihood information by using a first conversion table, a decoder which decodes the first likelihood information, a controller which outputs a decoding result of the decoder when the decoder succeeds decoding, and a creator module which creates a second conversion table based on the decoding result when the decoder fails decoding. When the second conversion table is created, at least a part of the decoding result is converted to second likelihood information by using the second conversion table the second likelihood information is decoded.

A transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence.

A computer-implemented method for error-correction-encoding and encrypting of a file is provided. The file is split into at least two blocks. The first block is encrypted using a given encryption key. The encrypted first block is encoded twice using a first and second forward error correction code of the first block. Each subsequent block is encrypted by performing an algebraic operation. The encrypted block is encoded twice using a first and second forward error correction code for this block, wherein a cryptographic indexing function provides a set of indices used by the second forward error correction code to produce the second encoded chunk. The first encoded chunks of each encrypted block are outputted. The computer-implemented method enables secure transmission of a file content between low power devices.

Methods and Apparatus for processing data encoded by low density parity check (LDPC) in a communication system are disclosed herein. In one embodiment, a method performed by a first node is disclosed. The method comprises: encoding an information bit sequence based on an LDPC coding scheme to obtain an encoded bit sequence; generating a master bit sequence based on the encoded bit sequence; selecting a subset of the master bit sequence according to a rate matching rule to obtain a rate matched bit sequence; interleaving the rate matched bit sequence according to a predetermined index sequence to obtain a to-be-transmitted bit sequence; and transmitting the to-be-transmitted bit sequence to a second node.

Methods and Apparatus for processing data encoded by low density parity check (LDPC) in a communication system are disclosed herein. In one embodiment, a method performed by a first node is disclosed. The method comprises: encoding an information bit sequence based on an LDPC coding scheme to obtain an encoded bit sequence; generating a master bit sequence based on the encoded bit sequence; selecting a subset of the master bit sequence according to a rate matching rule to obtain a rate matched bit sequence; interleaving the rate matched bit sequence according to a predetermined index sequence to obtain a to-be-transmitted bit sequence; and transmitting the to-be-transmitted bit sequence to a second node.

Methods and Apparatus for processing data encoded by low density parity check (LDPC) in a communication system are disclosed herein. In one embodiment, a method performed by a first node is disclosed. The method comprises: encoding an information bit sequence based on an LDPC coding scheme to obtain an encoded bit sequence; generating a master bit sequence based on the encoded bit sequence; selecting a subset of the master bit sequence according to a rate matching rule to obtain a rate matched bit sequence; interleaving the rate matched bit sequence according to a predetermined index sequence to obtain a to-be-transmitted bit sequence; and transmitting the to-be-transmitted bit sequence to a second node.

A polar decoder kernal is described. The polar decoder kernal is configured to: receive one or more soft bits from a soft kernal encoded block having a block size of N and output one or more recovered kernal information bits from a recovered kernal information block having a block size of N. The polar decoder kernal comprises a decomposition of a polar code graph into an arbitrary number of columns depending on the kernal block size N.

The present disclosure provides a data shifting operation apparatus having multiple operation modes that includes a preprocessing circuit, a first and a second shifting circuits and a multiplexer. The preprocessing circuit stores an input data group, having a data amount equal to a desired data amount M, to an under-operation data group, having the data amount equal to a maximum usage data amount N, from a most significant bit, and receives a shift amount S to calculate a total shift amount. The first and the second shifting circuits respectively cyclically shift the under-operation data group for the shift amount and the total shift amount to generate a first and a second shifted data groups. The multiplexer selects S data from the most significant bit of the second shifted data group and (M−S) data from the (N−S)-th bit of the first shifted data group to output a final shifted data group.