A variable width barrel shifter. The variable width barrel shifter includes a first barrel shifter configured to receive a data vector of width M as input. The variable width barrel shifter further includes a second barrel shifter configured to receive the data vector of width M as input. The variable width barrel shifter includes an element-wise multiplexer coupled to the first and second barrel shifters. The element-wise multiplexer is configured to provide a shifted output of the data vector of width M by including a first portion of output from the second barrel shifter and a second portion of output from the first barrel shifter.

Systems and methods for performing open-loop quantum error mitigation using quantum measurement emulations are provided. The open-loop quantum error mitigation methods do not require the performance of state readouts or state tomography, reducing hardware requirements and increasing overall computation speed. To perform a quantum measurement emulation, an error mitigation apparatus is configured to stochastically apply a quantum gate to a qubit or set of qubits during a quantum computational process. The stochastic application of the quantum gate projects the quantum state of the affected qubits onto an axis, reducing a trace distance between the quantum state and a desired quantum state.

A receiver is arranged for receiving a signal comprising an interleaved symbol stream. The receiver comprises a convolutional deinterleaver comprising a plurality of delay portions each of which is arranged to delay symbols from the symbol stream from an input to an output by a different amount, the delay portions being arranged in a sequence. An input selector is configured to input the symbols from the symbol stream to the delay portions so that successive symbols are input in accordance with the sequence of the delay portions. An output selector configured to read the symbols from the delay portions by successively selecting the symbols from the outputs of the delay portions in accordance with the sequence of the delay portions to form a deinterleaved symbol stream.

A receiver is arranged for receiving a signal comprising an interleaved symbol stream. The receiver comprises a convolutional deinterleaver comprising a plurality of delay portions each of which is arranged to delay symbols from the symbol stream from an input to an output by a different amount, the delay portions being arranged in a sequence. An input selector is configured to input the symbols from the symbol stream to the delay portions so that successive symbols are input in accordance with the sequence of the delay portions. An output selector configured to read the symbols from the delay portions by successively selecting the symbols from the outputs of the delay portions in accordance with the sequence of the delay portions to form a deinterleaved symbol stream.

A method and apparatus for decoding quasi-cyclic LDPC codes using a vertical layered iterative message passing algorithm. The algorithm of the method improves the efficiency of the check node update by using one or more additional magnitudes, predicted with predictive magnitude maps, for the computation of messages and update of the check node states. The method allows reducing the computational complexity, as well as the storage requirements, of the processing units in the check node update. Several embodiments for the apparatus are presented, using one or more predictive magnitude maps, targeting significant savings in resource usage and power consumption, while minimizing the impact on the error correction performance loss.

A polar decoder kernal is described. The polar decoder kernal includes a processing unit having: at least one input configured to receive at least one input Logarithmic Likelihood Ratio, LLR; a logic circuit configured to manipulate the at least one input LLR; and at least one output configured to output the manipulated at least one LLR. The logic circuit of the processing unit includes only a single two-input adder to manipulate the at least one input LLR, and the input LLR and manipulated LLR are in a format of a fixed-point number representation that comprises a two's complement binary number and an additional sign bit.

A bit interleaving method involves applying a bit permutation process to a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N/M folding sections, each of the constellation words being associated with one of the F×N/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

An apparatus is provided which comprises at least one processor, at least one memory including computer program code, and the at least one processor, with the at least one memory and the computer program code, being arranged to cause the apparatus to at least perform generating a code block including information bits and parity bits, the parity bits being generated by performing a cyclic redundancy check on the information bits, determining the number of parity bits used in generating the code block based on an applied linear error correcting code base graph and/or based on the number of the information bits, and encoding the code block by using the applied linear error correcting code base graph.

A bit interleaving method involves applying a bit permutation process to a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N/M folding sections, each of the constellation words being associated with one of the F×N/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=┌n/w┐) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=┌n/w┐) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (b.sub.k,n) in each successive t=┌n/w┐ clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n−k bits adopt a complementary binary value.