Systems and methods which provide parallel processing of multiple message bundles for a codeword undergoing a decoding process are described. Embodiments provide low-latency segmented quasi-cyclic low-density parity-check (QC-LDDC) decoder configurations in which decoding process tasks are allocated to different segments of the low-latency segmented QC-LDPC decoder for processing multiple bundles of messages in parallel. A segmented shifter of a low-latency segmented QC-LDPC decoder implementation may be configured to process multiple bundles of a plurality of edge paths in parallel. Multiple bundles of messages of a same check node cluster (CNC) are processed in parallel. Additionally, multiple bundles of messages of a plurality of CNCs are processed in parallel.

Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low-density parity check (LDPC) codes, for example, using a parity check matrix having full row-orthogonality. An exemplary method for performing low-density parity-check (LDPC) decoding includes receiving soft bits associated to an LDPC codeword and performing LDPC decoding of the soft bits using a parity check matrix, wherein each row of the parity check matrix corresponds to a lifted parity check of a lifted LDPC code, at least two columns of the parity check matrix correspond to punctured variable nodes of the lifted LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which the at least two punctured variable nodes are both connected.

Apparatuses, systems, and techniques to perform and facilitate an interface for multi-user and/or multi-cell physical layer (PHY) signal processing pipelines in a fifth generation (5G) new radio (NR) network. In at least one embodiment, a software interface facilitates scalable execution of multi-user and/or multi-cell information by a 5G-NR PHY software library implementing one or more signal processing pipelines.

One example method includes obtaining L.sub.1 first decoding paths of an (i−1).sup.th group of to-be-decoded bits, where i is an integer, received data corresponds to P groups of to-be-decoded bits, and 1<i≤P, determining at least one second decoding path corresponding to each first decoding path, where a quantity of second decoding paths corresponding to each first decoding path is less than 2.sup.n, and where n is a quantity of information bits included in an i.sup.th group of to-be-decoded bits, and determining at least one reserved decoding path of the i.sup.th group of to-be-decoded bits in second decoding paths corresponding to the L.sub.1 first decoding paths. The at least one reserved decoding path includes a decoding result of the i.sup.th group of to-be-decoded bits.

A polar decoder circuit can execute successive cancellation list polar decoding on multiple threads concurrently. An LLR update engine of the polar decoder circuit and a sort engine of the polar decoder circuit can operate concurrently, with the LLR update engine computing updated path metrics for one codeword while the sort engine sorts candidates for one or more other codewords according to path metrics already computed by the LLR update engine. Threads corresponding to different codewords can cycle sequentially between the LLR update engine and the sort engine.

The disclosed systems, structures, and methods are directed to encoding and decoding information for transmission across a communication channel. The encoding method includes: distributing the information bits between m parallel polar codes such that each of the m parallel polar codes includes a subset of the information bits; splitting the subset of information bits in each of the m parallel polar codes into a protected information section and a full rate information section; protecting information bits in the protected information section of each of the m parallel polar codes; arranging a plurality of frozen bits in each of the m parallel polar codes; and generating a polar encoded codeword for each of the m parallel polar codes.

Systems and methods are provided for decoding data read from non-volatile storage devices. A method that may include decoding a first codeword read from a storage location of a non-volatile storage device using a first decoder without soft information, determining that the first decoder has failed to decode the first codeword, decoding the first codeword using a second decoder without soft information, determining that the second decoder has succeeded in decoding the first codeword, generating soft information associated with the storage location using decoding information generated by the second decoder and decoding a subsequent codeword from the storage location using the soft information associated with the storage location. The second decoder may be more powerful than the first decoder.

A processing circuit implements: an encoder configured to: supply k symbols of original data to a neural product encoder including M neural encoder stages, a j-th neural encoder stage including a j-th neural network configured by j-th parameters to implement an (n.sub.j,k.sub.j) error correction code (ECC), where n.sub.j is a factor of n and k.sub.j is a factor of k; and output n symbols representing the k symbols of original data encoded by an error correcting code; or a decoder configured to supply n symbols of a received message to a neural product decoder including neural decoder stages grouped into a l pipeline stages, an i-th pipeline stage of the neural product decoder including M neural decoder stages, a j-th neural decoder stage comprising a j-th neural network configured by j-th parameters to implement an (n.sub.j,k.sub.j) ECC; and output k symbols decoded from the n symbols of the received message.

A method for error correction comprises receiving data at a first device, and decoding, by decoder circuitry of the first device, the data. Decoding the data comprises determining a first error location within the data, and determining a first error magnitude within the data in parallel with determining the first error location. Decoding the data further comprises performing error correction to generate the decoded data based on the first error location and the first error magnitude. The method further comprises transmitting the decoded data to a second device.

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.