This application discloses decoding methods, apparatuses, and computer-readable storage media, which may be applied to a plurality of scenarios such as a metropolitan area network, a backbone network, and data center interconnection. An example method includes: obtaining syndromes corresponding to a plurality of codewords; grouping the syndromes into groups; and sorting priorities of each group of syndromes; and selecting, based on a priority sorting result of each group of syndromes, a syndrome for decoding.

An electronic device, configured to perform a series of low-density parity check, LDPC, decoding operations for a parity check matrix, PCM, derived from at least one basegraph having a plurality of rows, includes: two or more check node, CN, sub-processors having input-output (I-O) port(s); and a controller configured to activate a subset of the I-O port(s) based on a current LDPC decoding sub-step of the LDPC decoding operations and the basegraph. The CN sub-processors support: a first single LDPC decoding operation to perform LDPC decoding computations for two or more rows of the PCM that are derived from different orthogonal rows of the plurality of rows in the basegraph; and a second mode whereby two or more of CN sub-processors co-operate to perform LDPC decoding computations for two or more rows of the PCM that are derived from a single row in the basegraph.

An electronic device is configured to perform a series of low density parity check, LDPC, decoding operations that use at least one basegraph that comprises two or more columns, each column associated with a set of two or more soft bit values. The electronic device includes two or more rotators, each rotator-configured to rotate an order of a subset of two or more soft bit values of the set of two or more soft bit values of a column when activated in an LDPC decoding operation; wherein rotations associated with each column in each basegraph are performed by a particular one of the rotators-of the two or more rotators, wherein each rotator performs rotations for a set of one or more columns, with at least one of the rotators performing rotations for two or more columns in a same basegraph.

A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, each data block having a number of data bits. The decoding apparatus is configured to decode in parallel two or more codewords, which share a common data block, to determine error information associated with each codeword. For each error, the error information identifies a data block having the and associated error bit patterns. The decoding apparatus is configured to update the two or more codewords based on the identified data blocks having errors and the associated error bit patterns.

Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include generating a codeword based on a number of low density parity check (LDPC) codewords failing a LDPC decoding operation and performing a BCH decoding operation on the codeword.

An error correction device according to the technical idea of the present disclosure includes a syndrome generation circuit configured to receive data and generate a plurality of syndromes for the data, a partial coefficient generation circuit configured to generate partial coefficient information on a part of a coefficient of an error location polynomial by using the data while the plurality of syndromes are generated, an error location determination circuit configured to determine the coefficient of the error location polynomial based on the plurality of syndromes and the partial coefficient information, and obtain a location of an error in the data by using the error location polynomial, and an error correction circuit configured to correct the error in the data according to the location of the error.

A codeword is generated based on a segmentation transform and a Polarization-Assisted Convolutional (PAC) code that includes an outer convolutional code and a polar code, and based on separate encoding of respective different segments of convolutionally encoded input bits according to the polar code. Each segment of the respective segments includes multiple bits of the convolutionally encoded input bits for which the separate encoding of the segment is independent of the separate encoding of other segments. Separate decoding may be applied to segments of such a codeword to decode convolutionally encoded input bits corresponding to the separately encoded segments of the convolutionally encoded input bits.

The disclosed systems, structures, and methods are directed to encoding and decoding information for transmission across a communication channel. The encoding method includes: distributing the information bits between m parallel polar codes such that each of the m parallel polar codes includes a subset of the information bits; splitting the subset of information bits in each of the m parallel polar codes into a protected information section and a full rate information section; protecting information bits in the protected information section of each of the m parallel polar codes; arranging a plurality of frozen bits in each of the m parallel polar codes; and generating a polar encoded codeword for each of the m parallel polar codes.

A storage which, in operation, stores a first minimum value and a second minimum value each time a plurality of data are input. Round-robin comparison circuitry which, in operation, makes a magnitude comparison among the plurality of data. First selection comparison circuitry and second selection comparison circuitry which, in operation, make a magnitude comparison between the first minimum value and each of the plurality of data and a magnitude comparison between the second minimum value and each of the plurality of data, respectively. Judgment circuitry which, in operation, judges a new first minimum value and a new second minimum value on the basis of a comparison result from the round-robin comparison circuitry and comparison results from the first and second selection comparison circuitry.

Certain aspects of the present disclosure provide an efficiently decodable QC-LDPC code which is based on a base matrix, the base matrix being formed by columns and rows, the columns being dividable into one or more columns corresponding to punctured variable nodes and columns corresponding to non-punctured variable nodes. Apparatus at a transmitting side includes a encoder configured to encode a sequence of information bits based on the base matrix. Apparatus at a receiving side configured to receive a codeword in accordance with a radio technology across a wireless channel. The apparatus at the receiving side includes a decoder configured to decode the codeword based on the base matrix.