An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises MN sub-matrices, wherein each of the sub-matrices is a ZZ matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a second permutation network of a permutation circuit by removing a target first permutation layer from a first permutation layer according to a shift type of the check matrix, wherein the amount of a plurality of second permutation layers and the amount of the second nodes of each of the second permutation layers are set according to the default dimension value; and disposing a plurality of selectors on the second nodes of the constructed second permutation network of the permutation circuit.

A method begins by a storage unit of a dispersed storage network (DSN) receiving a lock request from a distributed storage (DS) processing unit associated with the DSN for an encoded data slice (EDS) of a set of encoded data slices (EDSs). The method continues with the storage unit determining whether a lock request has previously been granted for the EDS and when a lock request has not been previously granted for a slice name associated with the EDS, transmitting, by the storage unit, a favorable lock request response to the DS processing unit and locking the slice name associated with the EDS. The method continues with storage unit receiving a persist message indicating that the DS processing unit has received a write threshold number of favorable lock request responses for the set of EDSs.

A semiconductor system may be provided. The semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to perform an error correction operation. The second semiconductor device may be configured to perform an error correction operation. The semiconductor system may selectively operate the first or second semiconductor devices with regards to error correction operations based on a mode signal.

A method begins by one or more processing modules of one or more computing devices of a dispersed storage network (DSN) determining that dispersed error encoded data slices stored in a plurality of distributed storage units of the DSN are to be updated and then sending a plurality of lock requests respectively to the plurality of distributed storage units. The method continues with the processing modules receiving a response from a write threshold number of distributed storage units of the plurality of distributed storage units that a lock request has been granted by each of the write threshold number of distributed storage units and then sending a persist message to each of the write threshold number of distributed storage units from which the lock request has been granted.

A method and apparatus allows single port memory devices to be accessed as pseudo two port memory devices. An access table is created to map the single port memory device to a single port even bank and a single port odd bank. The single port memory device is then accessed based on the mapping. An initial number of entries from the access table are retrieved in order to read addresses in the memory device until a predetermined delay expires. Simultaneous operations are then performed to read from rows in the memory device and write to rows in the memory device. Once all memory addresses have been read, write operations are sequentially performed in rows of the memory device based on the remaining entries of the access table.

A device includes a memory and a controller coupled to the memory. The controller is configured to determine a first count of bits of a representation of data that are estimated to be erroneous and a second count of bits of the representation of data that have high estimated reliability and are estimated to be erroneous. The controller is further configured to modify at least one read parameter or at least one decode parameter based on the first count and the second count.

Systems and methods are provided for decoding a codeword using an iterative decoding process. The systems and methods include receiving a codeword comprising a plurality of symbols, and concurrently processing the received codeword with a detector and a decoder based in part on extrinsic information associated with the plurality of symbols to obtain updated extrinsic information. The systems and methods further include modifying the extrinsic information associated with the plurality of symbols based on the updated extrinsic information, and repeating the processing and modifying steps until a stopping criterion is met.

Methods and apparatus for decoding LDPC codes provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. In an embodiment, a configurable LDPC decoder, which supports many different LDPC codes having any sub-matrix size, comprises several independently addressable memories which are used to store soft decision data for each bit node. The decoder further comprises a number, P, of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is P.sub.CNB (where PP.sub.CNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than P.sub.CNB*q bits.

According to an example, a method for assigning redundancy in encoding data onto crossbar memory arrays is provided wherein each of said crossbar memory arrays include cells. The data may be allocated to a subset of the cells in multiple crossbar memory arrays. The redundancy for the data may then be assigned based on coordinates of the subset of cells within the multiple crossbar memory arrays onto which the data is allocated.