Patent classifications
H03M13/6572
HUFFMAN CORRECTION ENCODING METHOD AND SYSTEM, AND RELEVANT COMPONENTS
The present disclosure discloses a method for Huffman correction and encoding, a system and relevant components, wherein the method includes: obtaining a target data block in a target file; constructing a Huffman tree by using the target data block; determining whether a depth of the Huffman tree exceeds a preset value; and when the depth of the Huffman tree does not exceed the preset value, by using the Huffman tree, generating a first code table and encoding the target data block; or when the depth of the Huffman tree exceeds the preset value, by using a standby code table, encoding the target data block; wherein the standby code table is a code table of an encoded data block in the target file.
Method and apparatus for generating a decoding position control signal for decoding using polar codes
Disclosed are a method and apparatus for generating a decoding position control signal for decoding using polar codes. The method and apparatus for generating a decoding position control signal for decoding using polar codes according to an embodiment of the present disclosure include generating a decoding tree obtained by forming a plurality of nodes in a hierarchical structure for a polar-encoded codeword, decoding the codeword using a successive cancellation (SC) decoding technique, and generating control signal through a preset operation relationship based on a position of a bit returned during re-decoding among the decoded codeword.
DEPTH CODEC FOR REAL-TIME, HIGH-QUALITY LIGHT FIELD RECONSTRUCTION
Systems, methods, and articles of manufacture are disclosed that enable the compression of depth data and real-time reconstruction of high-quality light fields. In one aspect, spatial compression and decompression of depth images is divided into the following stages: generating a quadtree data structure for each depth image captured by a light field probe and difference mask associated with the depth image, with each node of the quadtree approximating a corresponding portion of the depth image data using an approximating function; generating, from the quadtree for each depth image, a runtime packed form that is more lightweight and has a desired maximum error; and assembling multiple such runtime packed forms into per-probe stream(s); and decoding at runtime the assembled per-probe stream(s). Further, a block compression format is disclosed for approximating depth data by augmenting the block compression format 3DC+(BC4) with a line and two pairs of endpoints.
Forward error correction coding using a tree structure
A transmitter generates an encoded vector by encoding a data vector, the encoded vector representing payload information and parity information. The encoding is mathematically equivalent to calculating three or more forward error correction (FEC) codewords from the data vector and then calculating the encoded vector from the codewords, at least one codeword being calculated from at least one recursion of a mathematical operation, and at least one codeword comprising more than 6 terms. The transmitter transmits a signal representing the encoded vector over a communication channel. A receiver determines a vector estimate from the signal and recovers the data vector from the vector estimate by sequentially decoding the codewords, wherein at least one codeword that is decoded earlier in the decoding enhances an estimate of at least one codeword that is decoded later in the decoding.
Circuitry and method for decomposable decoder
Decoder circuitry for an input channel having a data rate, where a codeword on the input channel includes a plurality of symbols, includes options to provide a first output channel having that data rate, and a plurality of second output channels having slower data rates. The decoder circuitry includes syndrome calculation circuitry, polynomial calculation circuitry, and search-and-correct circuitry. The syndrome calculation circuitry includes finite-field multipliers for multiplying each symbol by a power of a root of the field. Each multiplier other than a first multiplier multiplies a symbol by a higher power of the root than an adjacent multiplier. First-level adders add outputs of a number of groups of multipliers. A second-level adder adds outputs of the first-level adders to be accumulated as syndromes of the first output channel. Another plurality of accumulators accumulates outputs of the first-level adders, which after scaling, are syndromes of the second output channels.
Parity check circuit and memory device including the same
A parity check circuit may include a first signal combination unit for generating first to N.sup.th combination signals by combining first to N.sup.th signals, wherein a K.sup.th (K is a natural number of 2KN) combination signal of the first to N.sup.th combination signals is obtained by combining the first to K.sup.th signals of the first to N.sup.th signals, a parity check unit for detecting whether an error is present in the first to N.sup.th signals in response to the N.sup.th combination signal, a second signal combination unit for generating first to N.sup.th reconstruction signals by combining the first to N.sup.th combination signals, wherein a K.sup.th reconstruction signal of the first to N.sup.th reconstruction signals is obtained by combining a (K1).sup.th combination signal and the K.sup.th combination signal of the first to N.sup.th combination signals, and a signal storage unit for storing the first to N.sup.th reconstruction signals.
Encoding apparatus and encoding method
In an encoding method, data segments and encoding information which indicates encoding patterns each representing a set of data segments used for a predetermined encoding calculation are acquired. An encoded data piece is generated by performing the predetermined encoding calculation based on each encoding pattern, and is stored in the memory. A first encoding pattern for generating the encoded data piece is compared to a second encoding pattern for a next encoding calculation, and the next encoding calculation is performed by using the encoded data piece corresponding to the first encoding pattern when at least a part of the second pattern is common with the first encoding pattern.
Flexible-rate polar decoder-based communication systems and methods
A method for decoding polar codes based encoded data comprises receiving the polar codes based encoded data, determining a rate at which the data is encoded, based on the determined rate, selecting suitable implemented super nodes in a flexible-rate polar decoder, and decoding the polar codes based encoded data. A flexible-rate polar decoder is created by receiving polar codes corresponding to a set of desired overheads, generating, for each overhead, a binary tree using fast successive cancellation decoding, generating a unified binary tree by determining locations of super nodes within each binary tree, representing the determined locations having same node index among different binary trees as super locations in the unified binary tree, each super location including more than one super node, and implementing the unified binary tree on an application specific hardware structure to create the flexible-rate polar decoder.
FLEXIBLE-RATE POLAR DECODER -BASED COMMUNICATION SYSTEMS AND METHODS
A method for decoding polar codes based encoded data comprises receiving the polar codes based encoded data, determining a rate at which the data is encoded, based on the determined rate, selecting suitable implemented super nodes in a flexible-rate polar decoder, and decoding the polar codes based encoded data. A receiver in a communication system, including a flexible-rate polar decoder; and a controller configured to: receive the polar codes based encoded data; determine a rate at which the data is encoded; based on the determined rate, select suitable implemented super nodes in a flexible-rate polar decoder; and decode the polar codes based encoded data.
PARITY CHECK CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
A parity check circuit may include a first signal combination unit for generating first to N.sup.thcombination signals by combining first to N.sup.th signals, wherein a K.sup.th (K is a natural number of 2KN) combination signal of the first to N.sup.thcombination signals is obtained by combining the first to K.sup.th signals of the first to N.sup.thsignals, a parity check unit for detecting whether an error is present in the first to N.sup.thsignals in response to the N.sup.th combination signal, a second signal combination iO unit for generating first to N.sup.th reconstruction signals by combining the first to N.sup.th combination signals, wherein a K.sup.threconstruction signal of the first to N.sup.threconstruction signals is obtained by combining a (K1).sup.th combination signal and the K.sup.th combination signal of the first to N.sup.thcombination signals, and a signal storage unit for storing the first to N.sup.threconstruction signals.