Memories retain data blocks on which exclusive logical OR computation is performed, and selection circuits receive a selection signal and select two or more data blocks for use in exclusive logical OR computation from among a plurality of data blocks read from the memories on the basis of the selection signal, and XOR circuits (exclusive logical OR computation circuits) perform exclusive logical OR computation based on the two or more data blocks selected by the selection circuits.

In general, a minimum determination capability, adapted for determining one or more minimum values from a set of values, is provided. The minimum determination capability may enable, for a set of values, determination of a first minimum value representing a smallest value of the set of values and a second minimum value representing an approximation of a next-smallest value of the set of values. The minimum determination capability may enable, for a set of values where each of the values is represented as a respective set of bits at a respective set of bit positions, determination of a minimum value of the set of values based on a set of bitwise comparisons performed for the respective bit positions of the values.

A parity check circuit may include a first signal combination unit for generating first to N.sup.th combination signals by combining first to N.sup.th signals, wherein a K.sup.th (K is a natural number of 2KN) combination signal of the first to N.sup.th combination signals is obtained by combining the first to K.sup.th signals of the first to N.sup.th signals, a parity check unit for detecting whether an error is present in the first to N.sup.th signals in response to the N.sup.th combination signal, a second signal combination unit for generating first to N.sup.th reconstruction signals by combining the first to N.sup.th combination signals, wherein a K.sup.th reconstruction signal of the first to N.sup.th reconstruction signals is obtained by combining a (K1).sup.th combination signal and the K.sup.th combination signal of the first to N.sup.th combination signals, and a signal storage unit for storing the first to N.sup.th reconstruction signals.