An erroneous bit determining circuit and a method are provided. The method includes: respectively performing a Hamming operation for an information symbol having an even weight and an information symbol having an odd weight to acquire a check symbol configured for the information symbol having an even weight and a check symbol configured for the information symbol having an odd weight; and respectively generating corresponding code words based on the information symbol having an even weight, the information symbol having an odd weight and the check symbols configured therefor. In this way, information symbols having the same number of bits are corrected without increasing the number of check symbol bits, and thus symbol transmission rate is improved.

The present disclosure provides a circuit. The circuit includes a detection circuit, a correction circuit and an adjustment circuit. The detection circuit is configured to detect an initial logic state of an input signal, and to generate, in response to the initial logic state, a first signal with a first logic state. The correction circuit is configured to compare the first signal having the first logic state with a second signal having a second logic state, and to generate an enable signal according to the comparison. The adjustment circuit is configured to be enabled by the enable signal when the first logic state of the first signal is different from the second logic state of the second signal, to generate an adjustment signal to the detection circuit, in which the detection circuit is further configured to be adjusted according to the adjustment signal, to generate an adjusted first signal.

A quantum computing device is provided, including a logical qubit encoding surface including a plurality of plaquettes. Each plaquette of the plurality of plaquettes may include a plurality of measurement-based qubits. The plurality of measurement-based qubits may include four data qubits and a first ancilla qubit. The first ancilla qubit may be electrically connected to the four data qubits and a second ancilla qubit included in the logical qubit encoding surface.

The present disclosure provides a circuit. The circuit includes a detection circuit, a correction circuit and an adjustment circuit. The detection circuit is configured to detect an initial logic state of an input signal, and to generate, in response to the initial logic state, a first signal with a first logic state. The correction circuit is configured to compare the first signal having the first logic state with a second signal having a second logic state, and to generate an enable signal according to the comparison. The adjustment circuit is configured to be enabled by the enable signal when the first logic state of the first signal is different from the second logic state of the second signal, to generate an adjustment signal to the detection circuit, in which the detection circuit is further configured to be adjusted according to the adjustment signal, to generate an adjusted first signal.

The invention relates to a method and an apparatus for decoding a Low-Density Parity-Check (LDPC) code. The method includes the following steps, which is performed by an LDPC decoder including a variable-node calculation circuitry and a check-node calculation circuitry: A first-stage state entering when a codeword has been stored in a static random access memory (SRAM) is detected. The check-node calculation circuitry is arranged operably to perform a modulo 2 multiplication on the codeword and a parity check matrix to calculate a plurality of first syndromes in the first-stage state. A second-stage state is entered when the first syndromes indicate that the codeword obtained in the first-stage state is incorrect. The variable-node calculation circuitry is arranged operably to perform a bit flipping algorithm accordingly to generate variable nodes, and calculate second soft bits for the variable nodes in the second-stage state. The check-node calculation circuitry is arranged operably to perform the modulo 2 multiplication on the variable nodes and the parity check matrix to calculate second syndromes in the second-stage stage. A third-stage state is repeatedly entered when the second syndromes indicate that the variable nodes generated in the second-stage state are incorrect until a decoding succeeds or a total number of iterations of the third-stage state exceeds a threshold.

Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.

An improved layered decoding method for a low density parity check (LDPC) code and a device therefor are disclosed. Disclosed is the layered decoding method for an LDPC code, capable of determining whether decoding is successful by performing a syndrome check on each check node at every variable node update. In addition, the syndrome check can be performed by using reduced variable nodes, thereby reducing decoding power consumption and decoding time consumption.

Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.

Described is a decoder suitable for use with any communication or storage system. The described decoder has a modular decoder hardware architecture capable of implementing a noise guessing process and due to its dependency only on noise, the decoder design is independent of any encoder, thus making it a universal decoder. Hence, the decoder architecture described herein is agnostic to any coding scheme.

An apparatus and method therefor relate generally to a CRC engine. In such a CRC engine, a feed forward circuit is coupled to a feedback circuit. The feed forward circuit includes: an offset circuit configured to determine an offset value from header data; a look-up table circuit configured to select a seed value responsive to the offset value; a shifter circuit configured to successively load a zero padding and a payload in multiple byte blocks as aligned data with the zero padding leading the payload for a non-zero value of the offset value in a first of the multiple byte blocks having the zero padding and a first portion of the payload; and a CRC circuit configured to receive data zeroes to a seed port thereof and the aligned data to a data port thereof to provide an interim CRC value.