Various approaches to implementing digital loopback in a radio frequency (RF) system are disclosed. An example RF system includes a receiver that includes an ADC and a transmitter that includes a DAC. The apparatus includes multiple digital loopback circuits provided at different points between the digital domain processing of the receiver and the transmitter. Each digital loopback circuit may include a combiner and one or more weighing circuits, which make the circuit programmable. The combiner of a given digital loopback circuit is configured to combine a RX signal and a TX signal at a particular point of the digital domain processing of the receiver and the transmitter where said digital loopback circuit is implemented. The one or more weighting circuits are configured to define the how much of the TX signal and/or RX signal is used for said combination.

Approaches provide for determining spectral information for a communications signal, such as a wideband communications signal. For example, a communications signal (e.g., a wideband signal) is received at a set of analog-to-digital converters (ADCs). The output of the ADCs is divided into a set of segments. A center frequency for each segment is determined based on the segment bandwidth and a number of segments in the set. The segments can be filtered, buffered, and analyzed using at least one digital signal processing technique (e.g., Fast Fourier Transform (FFT) technique to generate a representation of the segments in the frequency domain. Thereafter, the spectrum of frequency components (i.e., the frequency-domain representation) of the segments can be used to determine the power spectral density of the communications signal for different resolutions based on a resolution mode of the system or other criteria of the system.

A reconfigurable, multi-band hybrid beamforming architecture is introduced. The present invention is related to a Cartesian-Combining architecture to efficiently implement RF beamforming for a single downconversion chain employing direct downconversion in which the Cartesian-Combining architecture is extended to hybrid beamforming and to heterodyne downconversion.

The present disclosure relates to a wireless device including a mobile industry processor interface (MIPI) bus, a baseband processing module, and a radio frequency (RF) front-end module. Herein, digital data signals are transmitted bi-directionally between the baseband processing module and the digital front-end module, and RF signals are transmitted bi-directionally between the digital front-end module and an antenna. Each digital data signal is related to a corresponding RF signal. The baseband processing module and the digital front-end module are coupled to the MIPI bus, which is configured to transmit digital control signals between the baseband processing module and the digital front-end module. There is no analog signal transmitted between the baseband processing module and the digital front-end module.

A precursor rejection filter is disclosed. A digital filter is coupled to receive packets from a data source. The filter may operate in one of a first mode or a second mode. In the first mode, the filter may receive communications packets. When operating in the second mode, the filter may receive sensing packets. Furthermore, when operating in the second mode, the filter may cause a precursor of the equivalent impulse response of the transmitter to be attenuated without attenuating the main lobe of the of the equivalent impulse response of the transmitter.

Apparatus and associated methods relate to implementing an analog auxiliary clock and data recovery (CDR) path to provide a high bandwidth CDR in a transceiver that supports both PAM4 and NRZ signaling. In an illustrative example, the auxiliary CDR path may include a phase-frequency detector (PFD)-based phase-locked loop (PLL) and a phase detector (PD)-based PLL. When the PFD-based PLL is locked to a reference clock signal of the transceiver, the PFD-based PLL may be then disabled and the PD-based PLL may be then enabled. Implementing the auxiliary CDR path may advantageously enable the transceiver to implement much larger parts per million (ppm) acquisition and tracking, and thus enable the transceiver to advantageously support new standards such as Peripheral Component Interconnect Express (PCIe) 5.0 and PCIe 6.0, for example.

A system of multiple concurrent receivers is described to process multiple narrow bandwidth wireless signals with arbitrary bandwidth and center frequency separation. These multiple receivers may provide a downconverted signal at the baseband frequency to process signal bandwidth using the lowest power consumption while using fully modular signal processing blocks operating at the low frequency. The concurrent receivers may operate from a single high frequency amplifier and may be derived from a low impedance point to reduce loading and improve scalability. The center frequency and bandwidth of each of the channels as well as phases of each of the channels may be independently reconfigured to achieve scalability, and on-chip test and calibration capability.

An apparatus of user equipment (UE) includes a radio integrated circuit (IC), an adjustable external low noise amplifier (eLNA) external to the radio IC, and processing circuitry. The radio IC includes a receive signal circuit path including an adjustable gain internal low noise amplifier (iLNA), and a transmit signal circuit path including a digital-to-analog converter (DAC) circuit configured to convert digital signals to analog baseband signals for transmitting. The processing circuitry is configured to provide digital values of the digital signals to the DAC circuit and initiate adjusting gain of one or both of the iLNA and the eLNA according to the digital values.

In one embodiment an apparatus includes: a mixer to downconvert a radio frequency (RF) spectrum including at least a first RF signal of a first channel of interest and a second RF signal of a second channel of interest to at least a first second frequency signal and a second second frequency signal; a first digitizer to digitize the first second frequency signal to a first digitized signal, the first digitizer configured to operate as a low-pass analog-to-digital converter (ADC); a second digitizer to digitize the second second frequency signal to a second digitized signal, the second digitizer configured to operate as a band-pass ADC; and a digital processor to digitally process the first digitized signal and the second digitized signal.

Aspects of the present disclosure are directed to radar apparatuses and methods involving the communication of data with radar signals. As may be implemented with one or more embodiments, a sequence of radar waveforms are transmitted as RF signals, the RF signals carrying communication data encoded onto a ramped radar carrier signal via phase-shift keying (PSK) modulation. Such modulation may utilize a modified, reduced-angle modulation with phase angles of less than . Object-reflected versions of the RF signals are received and demodulated by deramping the received object-reflected versions of RF signals using a linearized version of the radar waveforms (e.g., without PSK modulation). This approach can mitigate compression peak loss.