Systems, devices, and methods related to interpolation are provided. An example apparatus includes a slope calculator to calculate a slope value based on a first value and a second value associated with a function. The apparatus further includes a compander to compand the slope value to provide a companded slope value having a smaller bit-width than the calculated slope value. The apparatus further includes a multiplier to multiply the companded slope value by a third value to provide a correction value. The apparatus further includes an adder to add the correction value to the first value or the second value to provide an interpolated value associated with the function. Companding the slope value can reduce a bit-width of the multiplier, and thus may reduce power consumption and/or area.

An antenna system mounted on a vehicle according to the present invention may comprise: a first circuit board configured to be mountable to a metal frame; a second circuit board disposed so as to be spaced apart a predetermined distance from the first circuit board through a metal supporter; and an antenna configured to emit a signal transmitted from a power supply unit, said signal being transmitted through a space between the first circuit board and the second circuit board.

A physical layer transceiver, for connecting a host device to a wireline channel medium in which a signal component occurring at a particular time may cause interference at other times, includes a host interface for coupling to a host device, a line interface for coupling to the channel medium, and filter circuitry operatively coupled to the line interface to filter the interference caused by the signal component at the particular time and at the one or more other times. The filter circuitry includes at least one filter segment configured to operate at a first rate derived from a channel operating frequency to filter the signal component at the particular time, and at least one respective filter segment configured to operate at a respective additional rate different from the first rate. Respective delay elements allow each respective filter segment to filter the signal component at a one of the other times.

A physical layer transceiver, for connecting a host device to a wireline channel medium in which a signal component occurring at a particular time may cause interference at other times, includes a host interface for coupling to a host device, a line interface for coupling to the channel medium, and filter circuitry operatively coupled to the line interface to filter the interference caused by the signal component at the particular time and at the one or more other times. The filter circuitry includes at least one filter segment configured to operate at a first rate derived from a channel operating frequency to filter the signal component at the particular time, and at least one respective filter segment configured to operate at a respective additional rate different from the first rate. Respective delay elements allow each respective filter segment to filter the signal component at a one of the other times.

Various embodiments provide for deep learning-based architectures and design methodologies for an orthogonal frequency division multiplexing (OFDM) receiver under the constraint of one-bit complex quantization. Single bit quantization greatly reduces complexity and power consumption in the receivers, but makes accurate channel estimation and data detection difficult. This is particularly true for OFDM waveforms, which have high peak-to average (signal power) ratio in the time domain and fragile subcarrier orthogonality in the frequency domain. The severe distortion for one-bit quantization typically results in an error floor even at moderately low signal-to-noise-ratio (SNR) such as 5 dB. For channel estimation (using pilots), various embodiments use novel generative supervised deep neural networks (DNNs) that can be trained with a reasonable number of pilots. After channel estimation, a neural network-based receiver specifically, an autoencoder jointly learns a precoder and decoder for data symbol detection.

Various embodiments provide for deep learning-based architectures and design methodologies for an orthogonal frequency division multiplexing (OFDM) receiver under the constraint of one-bit complex quantization. Single bit quantization greatly reduces complexity and power consumption in the receivers, but makes accurate channel estimation and data detection difficult. This is particularly true for OFDM waveforms, which have high peak-to average (signal power) ratio in the time domain and fragile subcarrier orthogonality in the frequency domain. The severe distortion for one-bit quantization typically results in an error floor even at moderately low signal-to-noise-ratio (SNR) such as 5 dB. For channel estimation (using pilots), various embodiments use novel generative supervised deep neural networks (DNNs) that can be trained with a reasonable number of pilots. After channel estimation, a neural network-based receiver specifically, an autoencoder jointly learns a precoder and decoder for data symbol detection.

An aspect of the disclosure relates to an apparatus including an output driver, including: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); a second PMOS FET coupled in series with the first PMOS FET between an upper voltage rail and an output; a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and a second NMOS FET coupled in series with the first NMOS FET between the output and a lower voltage rail; a first predriver coupled to gates of the first and second PMOS FETs and first and second NMOS FETs; and a second predriver coupled to the gates of the first and second PMOS FETs and first and second NMOS FETs.

An aspect of the disclosure relates to an apparatus including an output driver, including: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); a second PMOS FET coupled in series with the first PMOS FET between an upper voltage rail and an output; a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and a second NMOS FET coupled in series with the first NMOS FET between the output and a lower voltage rail; a first predriver coupled to gates of the first and second PMOS FETs and first and second NMOS FETs; and a second predriver coupled to the gates of the first and second PMOS FETs and first and second NMOS FETs.

The disclosure relates to technology for shifting a frequency range of a signal. In one aspect, a circuit comprises a frequency mixer, a frequency synthesizer configured to generate an oscillator signal, a programmable driver, and a controller. The programmable driver is configured to receive the oscillator signal from the frequency synthesizer and to provide the oscillator signal to the oscillator input of the frequency mixer. The programmable driver is configured to have a variable drive strength. The controller is configured to control the drive strength of the programmable driver based on a frequency of the oscillator signal to adjust a rise time and a fall time of the oscillator signal at the oscillator input of the frequency mixer.

An electronic device may include wireless circuitry with a baseband processor, a transceiver circuit, a front-end module, and an antenna. The front-end module may include amplifier circuitry such as a low noise amplifier for amplifying received radio-frequency signals. The amplifier circuitry is operable in a non-carrier-aggregation mode and a carrier aggregation mode. The amplifier circuitry may include an input transformer that is coupled to multiple amplifier stages such as a common gate amplifier stage, a cascode amplifier stage, and a common source amplifier stage. The common gate amplifier stage may include switches for selectively activating a set of cross-coupled capacitors to help maintain input impedance matching in the non-carrier-aggregation mode and the carrier-aggregation mode. The common source amplifier stage may include additional switches for activating and deactivating the common source amplifier stage to help maintain the gain in the non-carrier-aggregation mode and the carrier-aggregation mode.