A shaping encoder capable of improving the performance of PCS in nonlinear optical channels by performing the shaping in two or more stages. In an example embodiment, a first stage employs a shaping code of a relatively short block length, which is typically beneficial for nonlinear optical channels but may cause a significant penalty in the energy efficiency. A second stage then employs a shaping code of a much larger block length, which significantly reduces or erases the penalty associated with the short block length of the first stage while providing an additional benefit of good performance in substantially linear optical channels. In at least some embodiments, the shaping encoder may have relatively low circuit-implementation complexity and/or relatively low cost and provide relatively high energy efficiency and relatively high shaping gain for a variety of optical channels, including but not limited to the legacy dispersion-managed fiber-optic links.

Mechanisms to reduce noise and/or energy consumption in PAM communication systems, utilizing conditional symbol substitution in each burst interval of a multi-data lane serial data bus.

Systems and devices are provided for receiving or transmitting IQ data (e.g., suitable for passband quadrature amplitude modulation (QAM)) over a wireline using pairs of baseband pulse amplitude modulation (PAM-n) signals. Encoding circuitry may map data from an input bit stream to IQ data that includes an in-phase component and a quadrature-phase component. Modulator circuitry may determine an in-phase PAM-n signal based on the in-phase component and a quadrature-phase PAM-n signal based on the quadrature-phase component. Driver circuitry may transmit the in-phase PAM-n signal and the quadrature-phase PAM-n signal across a wireline channel. The in-phase PAM-n signal may be different by 90° from the quadrature-phase PAM-n signal. This may enable a remote receiver on the wireline channel to detect the in-phase PAM-n signal independently of the quadrature-phase PAM-n signal.

Encoders and decoders for encoding and decoding data according to a coding scheme. The encoder converts N bits of input data into M voltage signals for transmission over M parallel wires to a decoder having one or two decoding stages that recover the N bits of data from the M voltage signals. The coding scheme is an N-bit, M-wire PAM-Q code in which each voltage signal w.sub.i has one of Q voltage levels I.sub.1-I.sub.Q, where I.sub.1<I.sub.2< . . . <I.sub.Q, and the different sets of M voltage signals for the different N-bit input values are permutations of a single set of M voltage signals. The decoder has a comparator stage. For the decoder having one other decoding stage, the other decoding stage is a computation stage or a logic stage that is before or after the comparator stage.

An illustrative receiver includes: a decision element that derives symbol decisions from a slicer input signal; an equalizer that converts a receive signal into the slicer input signal; a summer that combines the symbol decisions with the slicer input signal to produce an error signal; and a level finder that operates on said signals to determine thresholds at which each signal has a given probability of exceeding the threshold. One illustrative level finder circuit includes: a gated comparator and an asymmetric accumulator. The gated comparator asserts a first or a second gated output signal to indicate when an input signal exceeds or falls below a threshold with a programmable condition being met. The asymmetric accumulator adapts the threshold using up steps for assertions of the first gated output signal and down steps for assertions of the second gated output signal, with the up-step size being different than the down-step size.

Encoders and decoders for encoding and decoding data according to a coding scheme. The encoder converts N bits of input data into M voltage signals for transmission over M parallel wires to a decoder having one or two decoding stages that recover the N bits of data from the M voltage signals. The coding scheme is an N-bit, M-wire PAM-Q code in which each voltage signal w.sub.i has one of Q voltage levels l.sub.1-l.sub.Q, where l.sub.1<l.sub.2< . . . <l.sub.Q, and the different sets of M voltage signals for the different N-bit input values are permutations of a single set of M voltage signals. The decoder has a comparator stage. For the decoder having one other decoding stage, the other decoding stage is a computation stage or a logic stage that is before or after the comparator stage.

In a semiconductor integrated circuit, a first generation circuit generates a common mode voltage of a differential signal. A second generation circuit generates temperature information according to the common mode voltage. The temperature information is information corresponding to a characteristic of an amplifier circuit related to an ambient temperature. A correction circuit corrects a first reference voltage and a second reference voltage according to the temperature information. A comparator includes a first input node to which a first signal line is electrically connected; a second input node to which a second signal line is electrically connected; a third input node to which the corrected first reference voltage is input; and a fourth input node to which the corrected second reference voltage is input.

Methods, systems, and devices related to a memory system or scheme that includes a first memory device configured for low-energy access operations and a second memory device configured for storing high-density information and operations of the same are described. The memory system may include an array configured for high-density information and may interface with a host via a controller and a cache or another array of a relatively fast memory type. The memory system may support signals communicated according to one or several modulation schemes, including a modulation scheme or schemes that employ two, three, or more voltage levels (e.g., NRZ, PAM4). The memory system may include, e.g., separate channels configured to communicate using different modulation schemes between a host and between memory arrays or memory types within the memory system.

A signal analysis method for determining at least one perturbance component of an input signal is described, wherein the perturbance is associated with at least one of jitter and noise. The signal analysis method includes: receiving and/or generating probability data containing information on a collective probability density function of a random perturbance component of the input signal and an other bounded uncorrelated (OBU) perturbance component of the input signal; determining a standard deviation of the random perturbance component based on the probability data; determining a random perturbance probability density function being associated with the random perturbance component based on the standard deviation; and determining an OBU perturbance probability density function being associated with the OBU perturbance component, wherein the OBU perturbance probability density function is determined based on the probability data and based on the probability density function that is associated with the random perturbance component. Further, a measurement instrument is described.

Communication systems are described that use signal constellations, which have unequally spaced (i.e. ‘geometrically’ shaped) points. In many embodiments, the communication systems use specific geometric constellations that are capacity optimized at a specific SNR. In addition, ranges within which the constellation points of a capacity optimized constellation can be perturbed and are still likely to achieve a given percentage of the optimal capacity increase compared to a constellation that maximizes d.sub.min, are also described. Capacity measures that are used in the selection of the location of constellation points include, but are not limited to, parallel decode (PD) capacity and joint capacity.