An illustrative receiver includes: a decision element that derives symbol decisions from a slicer input signal; an equalizer that converts a receive signal into the slicer input signal; a summer that combines the symbol decisions with the slicer input signal to produce an error signal; and a level finder that operates on said signals to determine thresholds at which each signal has a given probability of exceeding the threshold. One illustrative level finder circuit includes: a gated comparator and an asymmetric accumulator. The gated comparator asserts a first or a second gated output signal to indicate when an input signal exceeds or falls below a threshold with a programmable condition being met. The asymmetric accumulator adapts the threshold using up steps for assertions of the first gated output signal and down steps for assertions of the second gated output signal, with the up-step size being different than the down-step size.

An illustrative receiver includes: a decision element that derives symbol decisions from a slicer input signal; an equalizer that converts a receive signal into the slicer input signal; a summer that combines the symbol decisions with the slicer input signal to produce an error signal; and a level finder that operates on said signals to determine thresholds at which each signal has a given probability of exceeding the threshold. One illustrative level finder circuit includes: a gated comparator and an asymmetric accumulator. The gated comparator asserts a first or a second gated output signal to indicate when an input signal exceeds or falls below a threshold with a programmable condition being met. The asymmetric accumulator adapts the threshold using up steps for assertions of the first gated output signal and down steps for assertions of the second gated output signal, with the up-step size being different than the down-step size.

A jitter determination method for determining at least one jitter component of an input signal is described, wherein the input signal is generated by a signal source, comprising: receiving and/or generating probability data containing information on a collective probability density function of a random jitter component of the input signal and a other bounded uncorrelated jitter component of the input signal; determining a standard deviation of the random jitter component based on the probability data; determining a RJ probability density function associated with the random jitter component based on the standard deviation; and determining a OBUJ probability density function associated with the other bounded uncorrelated jitter component, wherein the OBUJ probability density function is determined based on the probability data and based on the probability density function that is associated with the random jitter component. Further, a measurement instrument is described.

A waveform correction apparatus includes a receiver configured to receive a first signal and a second signal from a signal transmission apparatus, the first signal being a PAM4 signal having a data pattern of a bit array in which gray coding is performed, and the second signal being a PAM4 signal having a data pattern of a bit array in which the gray coding is not performed, and a processor coupled to the receiver and configured to adjust a number of taps in an equalizer based on a difference between correct count values of forward error correction performed on the respective data patterns of the first signal and the second signal.

A hybrid voltage mode (VM) and current mode (CM) four-level pulse amplitude modulation (PAM-4) transmitter circuits (a.k.a. drivers) is calibrated using a configurable replica circuit and calibration control circuitry. The replica circuit includes an on-chip termination impedance to mimic a receiver's termination impedance. The amount of level enhancement provided by the current mode circuitry is calibrated by adjusting the current provided to the output node and sunk from the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving an intermediate PAM-4 level. After the level enhancement has been set, the non-linearity between levels is calibrated by adjusting the amount of current provided to the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving a maximum output voltage level.

A communication system in which a constellation employing partially anti-symmetric amplitude labels is used to transmit probabilistically shaped amplitudes such that said amplitudes are also used to determine the signs applied thereto for transmission. In an example embodiment, a data transmitter is configured to use a suitable logic function (e.g., an XOR function) to place the parity generated by an FEC code into a selected amplitude bit while using the partially anti-symmetric amplitude labels to avoid placing the parity into the sign bits of the transmitted constellation symbols. In some embodiments, the FEC code can be a low-density parity-check code. Some embodiments are compatible with layered FEC coding, e.g., employing an outer FEC code and an inner FEC code. In some embodiments, FEC coding may be optional. Some embodiments can advantageously be used in communication systems relying on DMT modulation, such as the systems providing DSL access over copper wiring.

Methods, systems, and devices related to a memory system or scheme that includes a first memory device configured for low-energy access operations and a second memory device configured for storing high-density information and operations of the same are described. The memory system may include an array configured for high-density information and may interface with a host via a controller and a cache or another array of a relatively fast memory type. The memory system may support signals communicated according to one or several modulation schemes, including a modulation scheme or schemes that employ two, three, or more voltage levels (e.g., NRZ, PAM4). The memory system may include, e.g., separate channels configured to communicate using different modulation schemes between a host and between memory arrays or memory types within the memory system.

A signal analysis method for determining at least one perturbance component of an input signal is described, wherein the perturbance is associated with at least one of jitter and noise. The signal analysis method includes: receiving and/or generating probability data containing information on a collective probability density function of a random perturbance component of the input signal and an other bounded uncorrelated (OBU) perturbance component of the input signal; determining a standard deviation of the random perturbance component based on the probability data; determining a random perturbance probability density function being associated with the random perturbance component based on the standard deviation; and determining an OBU perturbance probability density function being associated with the OBU perturbance component, wherein the OBU perturbance probability density function is determined based on the probability data and based on the probability density function that is associated with the random perturbance component. Further, a measurement instrument is described.

A hybrid voltage mode (VM) and current mode (CM) four-level pulse amplitude modulation (PAM-4) transmitter circuits (a.k.a. drivers) is calibrated using a configurable replica circuit and calibration control circuitry. The replica circuit includes an on-chip termination impedance to mimic a receiver's termination impedance. The amount of level enhancement provided by the current mode circuitry is calibrated by adjusting the current provided to the output node and sunk from the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving an intermediate PAM-4 level. After the level enhancement has been set, the non-linearity between levels is calibrated by adjusting the amount of current provided to the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving a maximum output voltage level.

A PAM (Pulse Amplitude Modulation) modulator driver is configured to receive a PAM input signal having N input amplitude levels and provide a PAM output signal having N output amplitude levels, where N is an integer. The PAM modulator driver circuit configured to electrically adjust amplitude levels in the PAM output signal.