An illustrative receiver includes: a decision element that derives symbol decisions from a slicer input signal; an equalizer that converts a receive signal into the slicer input signal; a summer that combines the symbol decisions with the slicer input signal to produce an error signal; and a level finder that operates on said signals to determine thresholds at which each signal has a given probability of exceeding the threshold. One illustrative level finder circuit includes: a gated comparator and an asymmetric accumulator. The gated comparator asserts a first or a second gated output signal to indicate when an input signal exceeds or falls below a threshold with a programmable condition being met. The asymmetric accumulator adapts the threshold using up steps for assertions of the first gated output signal and down steps for assertions of the second gated output signal, with the up-step size being different than the down-step size.

An illustrative receiver includes: a decision element that derives symbol decisions from a slicer input signal; an equalizer that converts a receive signal into the slicer input signal; a summer that combines the symbol decisions with the slicer input signal to produce an error signal; and a level finder that operates on said signals to determine thresholds at which each signal has a given probability of exceeding the threshold. One illustrative level finder circuit includes: a gated comparator and an asymmetric accumulator. The gated comparator asserts a first or a second gated output signal to indicate when an input signal exceeds or falls below a threshold with a programmable condition being met. The asymmetric accumulator adapts the threshold using up steps for assertions of the first gated output signal and down steps for assertions of the second gated output signal, with the up-step size being different than the down-step size.

The present invention relates to a 5th-generation (5G) or pre-5G communication system to be provided in order to support a higher data transmission rate than a beyond 4th-generation (4G) communication system such as long term evolution (LTE). The present invention relates to a signal transmission method of a radio frequency (RF) processing device, the method comprising the steps of: generating a pulse signal including a control signal and a clock signal for obtaining synchronization with another RF processing device, which is connected through an interface; and transmitting, to the another RF processing device, at least one from among the pulse signal, a RF signal for communication with a base station, and a power signal for supplying power to the another RF processing device, wherein the clock signal and the control signal are assigned to different time units, and the pulse signal, the RF signal and the power signal are signals of different frequency bands.

To detect an error in pulse width in a communication scheme that identifies a start position of a message or expresses a data value using a pulse width of a pulse included in the message, provided is a receiving apparatus including a receiving section that receives a message including a synchronization pulse having a predetermined pulse width and a first data pulse having a pulse width corresponding to a value of first data; and an error detecting section that detects an error in response to the number of non-synchronization pulses that are consecutive after the synchronization pulse being outside a predetermined number range.

An amplifier circuit acting as a line driver in a line between a central station and field devices connected thereto comprising: a DC/DC converter integrated in the circuit as a power stage comprising a DC/pulse converter with two electrically isolated switching stages; a logic block preceding the converter, generating control signals for the switches from a PWM signal and feeding them into the converter in an electrically isolated manner using drivers; a priority block generating the PWM signal; a first and a second controller. The priority block forwards output from the first or second controller. The first controller generates a fault signal based on a voltage limit and an output voltage fed back within the amplifier circuit via a feedback path. The second controller generates a fault signal based on a current limit and the output current. The central station defines the current limit and the voltage limit.

A device for detecting an audio interface includes a processing unit, a first audio interface transmitting circuit, and a second audio interface transmitting circuit. The processing unit is utilized to generate a clock signal and a word select (WS) signal. The first audio interface transmitting circuit is utilized to generate a first audio data according to the clock signal. The second audio interface transmitting circuit is utilized to generate a second audio data according to the clock signal and the WS signal. The processing unit switches to the first audio interface transmitting circuit if a voltage potential of the WS signal remains at a high voltage level or remains at a low voltage level longer than a predetermined period. The processing unit switches to the second audio interface transmitting circuit if the voltage potential of the WS signal changes during the predetermined period.

A power supply apparatus is provided including a housing, at least one battery receptacle for receiving at least one removable battery pack, an inverter that converts a direct-current (DC) signal from the at least one battery pack to an alternating-current (AC) signal, and a controller that applies a pulse-width modulation (PWM) signal to the inverter to shape the AC signal with a lower harmonic distortion relative to a square wave. For each full cycle of the AC signal, the controller sets the duty cycle to approximately 100% within a first period corresponding to a peak area of the AC signal, to less than approximately 100% but greater than approximately 0% within a second period in which the AC signal transitions from the peak to a zero-cross following the first period, and to 0% within a third period corresponding to the zero-cross of the AC signal following the second period.

The disclosure relates to a range-classifying-module for a radio receiver, the range-classifying-module configured to: receive a signal representative of a chirp from a transmitter, determine the presence of one or more pulses in the received signal; and classify the receiver as either proximal to or distal from the transmitter based on: one or more characteristics of the one or more pulses; in addition to a time-of-arrival of the one or more pulses.

The present invention is directed to a portable power supply system. The system is capable of converting DC power from one or more removable, rechargeable battery packs to AC power for corded power tools and appliance. The system is also capable of receiving AC power from an AC power supply and converting the AC power to DC power and using the DC power to charge the removable, rechargeable battery packs. The system includes a heat sink to assist in dissipating heat generated by various electronic components in the system. The heat sink also serves as a structural element to provide structural support to a housing of the system.

A programmable logic device, such as a field programmable gate array (FPGA), is disclosed that allows for both high speed and low speed signal processing using the existing high speed transceiver. The programmable logic of the device may be programmed to include a sampling logic block that determines the low speed bit patterns from a device under test (DUT). The logic may further include a bit replication logic block that replicates bits such that the output of the device's high speed transceiver looks like a low speed signal to the DUT. The device, therefore, can communicate with the DUT at both the high and low speeds without the need for intermediate hardware.