Systems and methods for payload transport for simple pulse division multiplexed (PDM) devices provide for simple PDM devices to have a phase-locked loop (PLL) that operates at a frequency corresponding to an audio rate on an associated audio bus. Additional parameters are defined relative to a starting synchronization event. The parameters inform a simple PDM device from which bit slots to extract data or into which bit slots to write data. In a further exemplary aspect, a low-cost delay-locked loop (DLL) is used to assist the simple PDM device in calculating the designated bit slots.

Wireless communications systems and methods related to communicating a sequence-based signal in a frequency spectrum are provided. A first wireless communication device obtains a configuration for communicating a sequence-based signal in the frequency spectrum. The configuration indicates resources in a frequency spectrum and a frequency distribution mode of the resources. The first wireless communication device communicates the sequence-based signal with a second wireless communication device in the frequency spectrum based on the configuration. The sequence-based signal includes at least one of a physical uplink control channel (PUCCH) signal or a physical random access channel (PRACH) signal. The frequency distribution mode indicates at least one of a frequency interlaced structure, a frequency comb structure, or a frequency mini-interlaced structure.

A system that switches between a clock signal from a first line card and a clock signal from a second line card based on information transmitted from the first line card and the second line card on timing signals is presented. Some methods include receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card; receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card; producing a clock signal from the first pulse-width modulated clock signal; and switching to producing the clock signal from the second pulse-width modulated clock signal based on the information in the first pulse-width modulated clock signal.

An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

To detect an error in pulse width in a communication scheme that identifies a start position of a message or expresses a data value using a pulse width of a pulse included in the message, provided is a receiving apparatus including a receiving section that receives a message including a synchronization pulse having a predetermined pulse width and a first data pulse having a pulse width corresponding to a value of first data; and an error detecting section that detects an error in response to the number of non-synchronization pulses that are consecutive after the synchronization pulse being outside a predetermined number range.

A power line communication apparatus includes a drive block including an actuator control circuit and a drive circuit and a communication block. The actuator control circuit generates a control pulse for controlling an actuator, and controls a transition timing of the control pulse during an operation period set within a communication cycle by a communication clock. The drive circuit controls a driving current of the actuator supplied from a DC power source through a power line based on the control pulse in which the transition timing is controlled. The communication block generates the communication clock, and modulates a current flowing through the power line in response to data to be transmitted during a signal transmission period different from the operation period, set within the communication cycle.

An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.