H04J3/04

Radio communication apparatus

Provided is a radio communication apparatus including a radio communication unit that performs radio communication with another radio communication apparatus, and a control unit that controls processing of adding information which can be used for communication by the another radio communication apparatus which is a transmission destination to a frame within such a range that transmission is possible using an assigned radio resource.

DATA TRANSMISSION METHOD, APPARATUS, AND SYSTEM, AND COMPUTER-READABLE STORAGE MEDIUM
20240089020 · 2024-03-14 ·

This application discloses a data transmission method. The method includes: performs bit multiplexing to obtain a plurality of third data streams based on a plurality of first data streams and a plurality of second data streams, where the first data stream and the second data stream belong to different virtual lane groups; and transmits the plurality of third data streams to a second module, to enable the second module to obtain a plurality of fourth data streams based on the plurality of third data streams, where any fourth data stream is obtained by performing bit multiplexing on any second quantity of third data streams in the plurality of third data streams. Bit multiplexing is performed on the obtained data streams, so that the method can improve a transmission rate of the data stream and reduce a frame loss ratio of a system.

Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit of a memory controller
11901961 · 2024-02-13 · ·

A method, for calibrating signal processing devices in an interface circuit coupled to a host device, comprises: negotiating with the host device in a link up process about an operation mode for the interface circuit to operate in a calibration procedure; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device in the calibration procedure. The first signal processing device is disposed on a receiving signal processing path and configured to process a received signal and the second signal processing device is disposed on a transmitting signal processing path and configured to process a transmitting signal, and the interface circuit is configured to operate based on the operation mode in the calibration procedure.

Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit of a memory controller
11901961 · 2024-02-13 · ·

A method, for calibrating signal processing devices in an interface circuit coupled to a host device, comprises: negotiating with the host device in a link up process about an operation mode for the interface circuit to operate in a calibration procedure; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device in the calibration procedure. The first signal processing device is disposed on a receiving signal processing path and configured to process a received signal and the second signal processing device is disposed on a transmitting signal processing path and configured to process a transmitting signal, and the interface circuit is configured to operate based on the operation mode in the calibration procedure.

Phase rotator

The present disclosure relates to phase alignment, in particular to phase alignment circuitry (and parts thereof) for example for use in a multiplexer or other circuitry in which data is transmitted from one stage to another. Consideration is given to phase detection and phase rotation. Such circuitry may be implemented as integrated circuitry, for example on an IC chip.

Configurable modem architecture for satellite communications

In some implementations, a communication device, includes a printed circuit board comprising conductors routed to support a plurality of different configurations of modulation and/or demodulation functionality. The printed circuit board can have multiple analog output interfaces and one or more analog input interfaces, multiple digital network interfaces, and sockets for components including a controller, multiple processors, digital-to-analog converters (DACs), and an analog-to-digital converter (ADC). Various processor sockets are interconnected to support the processors in different sockets selectively being used for different functions, e.g., as a modulator, burst processor, channelizer, etc.

CIRCUIT STRUCTURE FOR EFFICIENTLY DEMODULATING FSK SIGNAL IN WIRELESS CHARGING DEVICE

A circuit structure for efficiently demodulating an FSK signal in a wireless charging device, comprising a data sampling module, a period point counting module, a data distribution module, and a period point processing module. An input terminal of the period point counting module is connected to an output terminal of the data sampling module; an input terminal of the data distribution module is connected to an output terminal of the period point counting module; and an input terminal of the period point processing module is connected to an output terminal of the data distribution module.

Method and device for processing information

The embodiments of disclosure disclose a method and device for processing information. The method includes that: according to a predefined rule, subframes of a first serving cell are divided into multiple subframe groups; a management mode is configured for each of the subframe groups; and according to the management mode configured for each of the subframe groups, information on the first serving cell is processed. By means of the embodiments of the disclosure, a problem that some downlink subframes in a serving cell cannot be scheduled is solved, and different requirements of all subframes can be met, thereby improving a performance of a system, and ensuring an efficiency of data transmission.

Distributed flexible scheduler for converged traffic

A distributed flexible scheduler that dynamically balances network and storage traffic across links is proposed. The scheduler takes into account the bandwidth requirements of workloads provisioned in a cluster and dynamically distributes the network traffic and the storage traffic accordingly. There are three schemes involved in the proposed distributed flexible scheduler. In a first approach of Equal Distribution, network and storage traffic is distributed evenly across the links. In a second approach of Storage Preferred distribution, the aggregate storage bandwidth requirements of workloads exceed the network bandwidth requirements. In a third approach of Network Preferred distribution, the aggregate network bandwidth requirements of workloads exceed the storage bandwidth requirements.

Signal conversion apparatus, signal restoration apparatus and information processing apparatus

According to an embodiment, a signal conversion apparatus includes a control information generator and a selector. The control information generator generates first control information based on rate information indicating transmission rates of original signals. The first control information designates a first timing at which each of the original signals is sampled. The selector selects each of the sampled signals at a timing based on the first timing. The original signal group includes a first original signal at a first transmission rate and a second original signal at a second transmission rate. The first transmission rate is higher than the second transmission rate. The frequency of allocating the first timing to the first original signal is higher than a frequency of allocating the first timing to the second original signal.