A method and a device of cyclic redundancy check are provided. The method includes determining a payload portion, the payload portion including at least one information field for carrying information bits; determining input bits for generating CRC bits, the input bits including information bits carried in a part or all of at least one information field; generating target CRC bits according to the input bits; generating control information including the payload portion and the target CRC bits.

Rapid channel failure detection and recovery in wireless communication networks is needed in order to meet, among other things, carrier class Ethernet channel standards. Thus, resilient wireless packet communications is provided using a physical layer link aggregation protocol with a hardware-assisted rapid channel failure detection algorithm and load balancing, preferably in combination. This functionality may be implemented in a Gigabit Ethernet data access card with an engine configured accordingly. In networks with various topologies, these features may be provided in combination with their existing protocols.

Method and apparatus for transmission and reception of a Greenfield preamble are provided. In the method and apparatus, the Greenfield preamble may be a single user (SU) preamble or a multi user (MU) preamble. As an MU preamble, the Greenfield preamble includes a short training field (STF), a first long training field (LTF), a first signal (SIG) field, at least one additional LTF, and a second SIG field. Additionally, the Greenfield preamble may be utilized for efficient transmission and reception of control information to wireless devices, whereby the control information may be indicated using the STF, the first LTF, or the first or second SIG fields.

A particular overall architecture for transmission over a bonded channel system consisting of two interconnected MoCA (Multimedia over Coax Alliance) 2.0 SoCs (Systems on a Chip) and a method and apparatus for the case of a “bonded” channel network. With a bonded channel network, the data is divided into two segments, the first of which is transported over a primary channel and the second of which is transported over a secondary channel.

A polar encoder comprises an input, an output and a processor operatively connected to the input and to the output. The input either receives first, second and third codewords, or receives information bits used by the processor for generating first, second and third probabilistic constellation shaping codewords. The processor combines the first and second codewords, to produce a first modulation symbol bit, combines the first and third codewords to produce a second modulation symbol bit, and combines the first, second and third codewords to produce a third modulation symbol bit. The output forwards the modulation symbol bits to a bit to symbol mapper. The polar encoder may be included in a transmitter that further comprises the bit to symbol mapper receiving the modulation symbol bits and generating modulation symbols, and a modulator modulating a carrier using the modulation symbols.

A method of data processing is applied to a communications device including a first sublayer. A physical sublayer is added above a physical coding sublayer (PCS) of a physical layer, and the physical sublayer is connected to media independent interfaces (xMIIs) with different Ethernet rates. Data signals from different media access control clients (MAC) are interleaved using the physical sublayer. Then, a tx_cmd command is used to instruct the PCS to correspondingly encode an xMII signal. Finally, an encoded xMII signal is sent through a port. According to this method, an encoding function of the PCS may continue to be used, to decouple interleaving from encoding and perform the interleaving through an xMII interface. In this case, port channelization can be implemented for ports with multiple rates, and transmission of a high-priority service is ensured when there is an excessively large quantity of service flows in a transmission process.

A method of processing a service in a transmitter, and including generating, by a hardware processor, a first media component and a second media component for the service; generating, by the hardware processor, signaling data for the service; time interleaving, by a time interleaver, the first media component, wherein the first media component is time-interleaved by column-wise writing actual Forward Error Correction (FEC) blocks including the first media component in a Time Interleaving (TI) memory and diagonal-wise reading the first media component in the actual FEC blocks from the TI memory, wherein one or more virtual FEC blocks are skipped during the diagonal-wise reading the written first media component, and wherein a number of the one or more virtual FEC blocks is equal to a difference between a number of the actual FEC blocks and a column number of the TI memory; generating, by a signaling generator, physical layer signaling information, wherein the physical layer signaling information includes first physical layer signaling information and second physical layer signaling information, wherein the first physical layer signaling information includes information for identifying a size of the second physical layer signaling information and wherein the second physical layer signaling information includes information for obtaining the column number of the TI memory; transmitting, by an antenna, the time-interleaved first media component, the physical layer signaling information and the signaling data through a broadcast network; and transmitting, by a network interface, the second media component to a receiver through a broadband network. Further, the signaling data transmitted through the broadcast network includes first timeline information for specifying a timeline of the first media component transmitted through the broadcast network and uniform resource location information for the second media component.

A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to generate a plurality of bit groups each of which is formed of a same number of bits, determine whether a number of the outer-encoded bits satisfies a predetermined number of bits required according to at least one of a code rate and a code length for Low Density Parity Check (LDPC) encoding, pads zero bits to some of the bits in the bit groups if the number of the outer-encoded bits is less than the predetermined number of bits, and maps the outer-encoded bits to remaining bits in the bit groups, based on a predetermined shortening pattern, thereby to constitute LDPC information bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the some of the bits, in which zero bits are padded, are included in some of the bit groups which are not sequentially disposed in the LDPC information bits.

Apparatuses, systems, and methods may determine a transport block size using a number of resource elements for sidelink data. The number of resource elements for the sidelink data is calculated based at least on a reference second stage Sidelink Control Information (SCI) overhead. The reference second stage SCI overhead is calculated using the reference coding rate, the reference beta offset, the reference PSFCH symbol number, the alpha value, and the second stage SCI payload size.

Described herein are, among other things, techniques, devices, and systems for streaming pixel data from a host computer to a wireless display device with low latency. In some embodiments, a user mode driver is executed in user mode of the host computer to configure a wireless network interface controller of the host computer to operate in a low latency manner. The display device may use a Forward Error Correction (FEC) algorithm to reconstruct a frame from the data packets it receives from the host computer. Also disclosed are techniques for scrambling the transmission of a series of data packets using different antenna configurations, as well as setting a modulation and coding scheme (MCS) rate based at least in part on the amount of pixel data to be transmitted to the display device. The display device may comprise a head-mounted display (HMD) that renders virtual reality (VR) game imagery.