A system for transcoding a digital video stream using a transcoder includes receiving a digital video stream that includes an input video stream and extracting a first set of presentation time stamps from the input video stream which are stored in a table. The system transcodes the input video stream including the first set of presentation time stamps from an initial set of characteristics to a modified set of characteristics including a second set of presentation time stamps that are different from the first set of presentation time stamps. The system processes the second set of presentation time stamps of the transcoded video stream to determine if the second presentation time stamps include jitter, and based upon determining the second set of presentation time stamps include jitter modifying the second set of presentation time stamps based upon the first set of presentation time stamps in the table.

Methods and systems are described for measuring a vertical opening of a signal eye of a pulse amplitude modulated (PAM) signal received over a channel to determine a vertically-centered voltage decision threshold of a sampler receiving a sampling clock, determining channel-characteristic parameters indicative of a frequency response of the channel, determining a correctional vernier value from the channel-characteristic parameters, and generating a horizontally-centered voltage decision threshold that introduces a horizontal sampling offset in the sampling clock in a direction closer to a horizontal center of the signal eye by combining the vertically-centered voltage decision threshold and the correctional vernier value.

A scheme for noise floor de-embedding by identifying a link or relationship between noise floor from an oscilloscope and phase jitter impact on a toggling signal. The scheme uses phase or electrical spectrum and phase detection for noise floor recognition. The scheme de-embeds the impact from random noise and also removes deterministic noise or jitter from the oscilloscope. The scheme provides accurate jitter analysis for a circuit (e.g., clock data recovery circuit) after de-embedding noise floor for the oscilloscope.

A multi-lane transmitting apparatus includes lanes, and each lane includes a serializer circuit to convert parallel bits to serial bits. A clock signal generator generates a first clock signal having phases. A deserializer circuit converts serial bits to parallel bits. A Built-In Self-Test (BIST) circuit includes a signal generator circuit for generating a signal having bits in a defined pattern. A comparator circuit compares a pattern of bits of an output signal with the defined pattern. A BIST lane circuit monitors a status of the lanes. A BIST central circuit receives the status and determines if a number of lanes having an unmatched status is less than a threshold value. A phase extrapolator circuit adjusts a phase of the first clock signal when the number of the lanes is less than the threshold value.

A method for synchronizing a distributed application includes: transmitting, by an application backend, application data packets to an application frontend; transmitting, by the application backend, a synchronization request packet to the application frontend; retrieving, by the application backend, a backend timestamp from a server clock; retrieving, by the application frontend, a frontend timestamp from a terminal device clock and transmitting the retrieved frontend timestamp to the application backend; calculating, by the application backend, a time offset of the frontend timestamp from the retrieved backend timestamp and using the calculated time offset for synchronization; detecting, by a scheduler, an actual state of a communication connection and transmitting control data to the application backend; and adapting, by the application backend, transmission of synchronization request packets based on the control data indicating jitter of the synchronization request packets preventing the distributed application from being executed synchronously.

Disclosed herein are systems and methods for network traffic shaping and/or adjustment of discontinuous reception (DRX) cycles. A wireless device determines a delay between a time at which a packet is transmitted from a server, to a time of arrival of the packet at the wireless device. The wireless device determines jitter of packets arriving at the wireless device from the server. The wireless device sends a message corresponding to the determined delay and the determined jitter, to the server to perform shaping of packet traffic from the server to the wireless device according to a latency budget of the packet traffic. The wireless device adjusts a length of a discontinuous reception (DRX) cycle of the wireless client device, to align with and to receive the packet traffic shaped by the server.

A signal interpolation method is described. The method includes: receiving an analog input signal; digitizing the analog input signal received, thereby obtaining a digitized input signal having samples; determining a crossing of the digitized input signal with respect to a threshold that was set; and interpolating a signal between at least two successive samples, wherein the signal interpolated has two signal portions each having a linear slope, and wherein one of the signal portions crosses the threshold. A measurement instrument is also described.

A multi-lane transmitting apparatus includes lanes, and each lane includes a serializer circuit to convert parallel bits to serial bits. A clock signal generator generates a first clock signal having phases. A deserializer circuit converts serial bits to parallel bits. A Built-In Self-Test (BIST) circuit includes a signal generator circuit for generating a signal having bits in a defined pattern. A comparator circuit compares a pattern of bits of an output signal with the defined pattern. A BIST lane circuit monitors a status of the lanes. A BIST central circuit receives the status and determines if a number of lanes having an unmatched status is less than a threshold value. A phase extrapolator circuit adjusts a phase of the first clock signal when the number of the lanes is less than the threshold value.

A first communications device may use one or a plurality of communications connections in parallel for a communications session between the first communications device and the second communications device. The first device makes decisions as to the number of connections to use, the level of error correcting code to use, and/or the level of packet redundancy to use based on test scores corresponding to one or more communications session connections. The first communications device generates a first test score corresponding to a first communications session connection based on a test performed over a first test path between the first communications device and a test server, said first communications session connection and the first test path sharing a common link, e.g., a common wireless link between the first device and an access point. The first device may generate and use an overall connection score corresponding to a plurality of session connections.

There are provided a data comparison unit that detects an FEC symbol error of a signal under test output from a DUT in accordance with an input of a jitter signal, an error counting unit that counts the number of detected FEC symbol errors for each codeword for each phase modulation amount, a codeword classification unit that classifies a plurality of codewords included in the signal under test into a plurality of groups based on the counted number of FEC symbol errors, a codeword number counting unit that counts the number of codewords in each group for each phase modulation amount, and a display control unit that controls a display of a first graph having a horizontal axis as the phase modulation amount and a vertical axis as a ratio of the number of codewords in each group, on a display screen.