There are provided a data comparison unit that detects an FEC symbol error of a signal under test output from a DUT in accordance with an input of a jitter signal, an error counting unit that counts the number of detected FEC symbol errors for each codeword for each phase modulation amount, a codeword classification unit that classifies a plurality of codewords included in the signal under test into a plurality of groups based on the counted number of FEC symbol errors, a codeword number counting unit that counts the number of codewords in each group for each phase modulation amount, and a display control unit that controls a display of a first graph having a horizontal axis as the phase modulation amount and a vertical axis as a ratio of the number of codewords in each group, on a display screen.

Provided is a display driving circuit. The display driving circuit includes a clock data recovery circuit configured to receive a data signal and generate a clock signal and a first output data signal, an eye margin test circuit configured to sample the data signal by using the clock signal, based on a vertical measurement voltage and generate a second output data signal, and a bit error check circuit configured to measure a bit error rate of the data signal, based on the first output data signal and the second output data signal, wherein the clock data recovery circuit includes a jitter generator configured to generate jitter of the clock signal such that a jitter amplitude varies according to a horizontal control signal.

This information processing system inputs/outputs data normally, even when a serial communication bus is extended by network communication. The information processing system is provided with: a device; a device control unit for controlling the device; a device interface unit which interfaces with the device control unit; an information processing device provided with an application interface unit which interfaces with an application; a channel establishment unit which connects, via a communication unit, the application interface unit and the device interface unit, and establishes a control channel and a data channel between the application and the device; and an error suppression unit which suppresses the occurrence of error in data transfer over the channel established by the channel establishment unit.

A method of measuring linearity characteristics of a delay line may be provided. The method may include generating an output signal from a receiver including a delay line. The method may also include measuring linearity characteristics of the delay line based on a target performance parameter of the output signal.

A method and apparatus for generating a probability density function eye are provided. The method preferably includes the steps of acquiring an input waveform, performing a clock data recovery in accordance with the input waveform to determine one or more expected transition times and defining a plurality of unit intervals of the input waveform in accordance with the one or more expected transition times. One or more values of one or more data points may then be determined in accordance with the input waveform in accordance with the one or more expected transition times, and a category for each unit interval in accordance with its state and its position within the input waveform may also be determined. One or more histograms may then be generated for the determined one or more values for each category of unit intervals.

A method of testing a data transmission and reception system comprises sending a test signal from a transmitter (14) of the system to a receiver (12) of the system, and analyzing the received signal. A duty cycle relationship is varied between the test signal and the timing signal used by the receiver of the system, and the effect of the duty cycle variation is analyzed. Varying the duty cycle relationship provides duty cycle distortion (DCD), and this can be considered as a form of embedded jitter insertion. This type of jitter can be measured relatively easily.

A route selection system includes a hub controller in communication with multiple network hubs of a first network domain in which each of the hubs are in communication with a corresponding multiple routers of a second network domain. The hub controller is executed to obtain at least one performance measurement associated with a route terminating at the network hub, generate a border gateway protocol (BGP) advertisement with a preference value that is proportional to the received performance measurement, and transmit the generated advertisement to the network hub, the network hub forwarding the advertisement to the router configured in the other network domain. Upon receipt of the advertisements, the second network domain selects one of the routers for processing the route through the second network domain according to the performance measurement included in the advertisement.

The present invention provides integrated circuit and apparatus having USB connector; the integrated circuit includes a signaling circuit and an interface for relaying signal between the USB connector and the signaling circuit, wherein an interconnect scheme of the signaling circuit is different from USB interconnect defined by USB specification; for example, a frequency adopted for signaling can be programmable, be lower than wireless band and/or be different from a frequency of USB SuperSpeed interconnect.

A semiconductor device including a comparison circuit configured to receive an input signal having n signal levels, where n is a natural number equal to or greater than three, and output n-1 first signals having two signal levels. The device includes a jitter compensation circuit configured to receive the n-1 first signals and compensate for at least one of a length of a period in which a signal level of at least one of the n-1 first signals transitions from a first signal level to a second signal level different from the first signal level, and a length of a period in which the signal level of the at least one of the n-1 first signals transitions from the second signal level to the first signal level, to output n-1 second signals.

A jitter measuring setup (10) comprises a signal generator (14), a sample-and-hold circuit (15), and the inventive all stochastic jitter measuring device (1) comprising signal acquisition means (2) and calculation means (3). The input signal of the sample-and-hold circuit (15) is generated by the signal generator (14). Furthermore, the output signal of the sample-and-hold circuit (15), respectively the input signal of the measuring device (1), is comprised of a superposition of the sampled input signal of the sample-and-hold circuit (15) and a cyclostationary random process.