H04L5/1407

Impedance matching for high speed signaling in memory system

Impedance matching circuitry is positioned on a signal line intermediate the terminals of the signal line in an integrated circuit. The impedance matching circuitry can include discrete components off the integrated circuit and on a substrate, e.g., a board. The impedance matching circuitry can operate to match the impedance of a signal line in the integrated circuit, e.g., a memory device such as a DRAM or DDR DRAM.

Retry disparity for control channel of a multimedia communication link

A multimedia system for data communications. A source device communicates data over a full duplex control channel of a multimedia communication link. The source device has a first link layer that retries unsuccessful data communications over the full duplex control channel until a first maximum retry limit of the first link layer is reached. A sink device communicates data over the full duplex control channel of the multimedia communication link. The sink device has a second link layer that retries unsuccessful data communications over the full duplex control channel until a second maximum retry limit of the second link layer is reached, where the second maximum retry limit is different than the first maximum retry limit.