Patent classifications
H04L5/1407
INDICATIONS OF CAPABILITIES FOR SELF-INTERFERENCE CANCELLATION
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit an indication of capabilities of the UE for self-interference cancellation at one or more center frequencies. The UE may receive an indication of a configuration, based at least in part on the indication of capabilities, associated with one or more subsequent communications. Numerous other aspects are described.
Indications of capabilities for self-interference cancellation
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit an indication of capabilities of the UE for self-interference cancellation at one or more center frequencies. The UE may receive an indication of a configuration, based at least in part on the indication of capabilities, associated with one or more subsequent communications. Numerous other aspects are described.
System and method for indicating preemption of transmissions
In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. In certain configurations, the apparatus may include an eMBB UE. The apparatus may monitor a single preconfigured mini-slot in each of a plurality of slots for a PI. The apparatus may receive the PI in the single preconfigured mini-slot of a first slot of the plurality of slots. In certain aspects, the PI may include a resource index associated with a reduced transmission power by the UE. In certain other aspects, the resource index may include one or more resources in a second slot. The apparatus may transmit at least one packet with the reduced transmission power on the one or more resources in the second slot or refraining from transmitting the at least one packet on the one or more resources in the second slot.
Managing a number of ethernet links
A method for managing a number of Ethernet links includes identifying a number of Ethernet links to utilize a number of channels of a cable based on a number of capabilities and a number of policies of a number of media access controllers (MACs) and a number of physical layer entities (PHYs), determining a number of Ethernet link types to be configured for the cable based on the capabilities and policies of the MACs and PHYs, negotiating a number of parameters to allow multi-channel ports of a number of nodes connected to the cable to establish communications through the Ethernet links based on the determined Ethernet link types and the utilized channels, and managing the cable configuration describing the MACs to be supported by the channels within the cable based on the policies.
Slave device for a serial synchronous full duplex bus system
A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.
SYSTEM AND METHOD FOR INDICATING PREEMPTION OF TRANSMISSIONS
In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. In certain configurations, the apparatus may include an eMBB UE. The apparatus may monitor a single preconfigured mini-slot in each of a plurality of slots for a PI. The apparatus may receive the PI in the single preconfigured mini-slot of a first slot of the plurality of slots. In certain aspects, the PI may include a resource index associated with a reduced transmission power by the UE. In certain other aspects, the resource index may include one or more resources in a second slot. The apparatus may transmit at least one packet with the reduced transmission power on the one or more resources in the second slot or refraining from transmitting the at least one packet on the one or more resources in the second slot.
SLAVE DEVICE FOR A SERIAL SYNCHRONOUS FULL DUPLEX BUS SYSTEM
A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.
Slave device for a serial synchronous full duplex bus system
A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.
Asymmetric full duplex communication including device power communication
An active transceiver circuit for transmission of a low bitrate data signal over and reception of a high bitrate data signal from a single ended transmission medium is provided. The active transceiver circuit includes an input port for receiving a low bitrate input data signal, an output port for delivering a high bitrate output data signal, a differential input/output port for launching a low bitrate data signal into the single ended transmission medium and for receiving a high bitrate data signal from the single ended transmission medium, a first and second single ended output driver adapted for each delivering, on their respective output nodes, the shaped low bitrate input data signal, and a high bitrate receiver for receiving the signals at output nodes of the first and second single ended output drivers, and for generating a high bitrate output data signal on the output port.
Asymmetric full duplex communication including device power communication
An active transceiver circuit for transmission of a low bitrate data signal over and reception of a high bitrate data signal from a single ended transmission medium is provided. The active transceiver circuit includes an input port for receiving a low bitrate input data signal, an output port for delivering a high bitrate output data signal, a differential input/output port for launching a low bitrate data signal into the single ended transmission medium and for receiving a high bitrate data signal from the single ended transmission medium, a first and second single ended output driver adapted for each delivering, on their respective output nodes, the shaped low bitrate input data signal, and a high bitrate receiver for receiving the signals at output nodes of the first and second single ended output drivers, and for generating a high bitrate output data signal on the output port.