Methods and systems are described for obtaining a plurality of BER-specific correction values by comparing a first set of BER values obtained by sampling, at a sampling instant near the center of a signaling interval, a non-DFE corrected received signal with a second set of BER values obtained by sampling a DFE-corrected received signal at the sampling instant. A set of eye-scope BER measurements are obtained, each eye-scope BER measurement having a sampling offset relative to the sampling instant, a voltage offset value representing a voltage offset applied to alter a decision threshold, and an eye-scope BER value. A set of DFE-adjusted eye-scope BER measurements are generated by using BER-specific correction values to adjust the voltage offset values of the eye-scope BER measurements.

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

A base station and the customer premises equipment (CPE) transceivers are configured to use a single master clock for all frequency conversions. The modem of each CPE has a clock output and that output is connected to the upconverter in the transceiver uplink or to both the upconverter and the downconverter as required.

Provided is a transmission/reception system that can implement miniaturization and a reduced number of wires for transmitting a signal between a sensor device and a reception device. The sensor device includes a data transmitting unit configured to transmit imaging data synchronized with a first clock signal to the reception device through a first signal transmission path, a clock signal transmitting unit configured to transmit a second clock signal with a lower frequency than the first clock signal to the reception device through a second signal transmission path, and a control signal communicating unit configured to communicate a control signal necessary for control of the first clock signal with the reception device through the second signal transmission path. The reception device includes a signal generating unit configured to generate the control signal on the basis of a comparison result of a comparison between a reference clock signal and any one of the second clock signal based on the first clock signal and the second clock signal transmitted from the sensor device through the second signal transmission path, and a control signal communicating unit configured to communicate the control signal with the sensor device through the second signal transmission path.

A method at a first device for synchronising a first clock of the first device to a second clock of a second device, includes receiving a first message comprising an identifier from a third device; generating a first timestamp in dependence on the time at which the first message is received at the first device according to the first clock; receiving a second message from the second device comprising the identifier and a second timestamp, the second timestamp having been generated in dependence on the time at which the second device received the first message from the third device according to the second clock; and adjusting the first clock in dependence on a time difference between a time indicated by the first timestamp and a time indicated by the second timestamp.

A clock synchronization packet exchanging method includes sending, by a first device in a Flexible Ethernet (FlexE) group, a first FlexE instance at a first physical layer (PHY), where the first FlexE instance includes a clock synchronization packet, and a second FlexE instance sent by the first device in the FlexE group at a second PHY also includes a clock synchronization packet. The clock synchronization packets are carried in a plurality of FlexE instances transmitted between a transmit end and a receive end in the FlexE group.

A system includes a first integrated circuit device, a second integrated circuit device, and a reference clock provided to the first and second integrated circuit devices. The first integrated circuit device detects a first edge of a first clock utilized by the first integrated circuit device, detects a second edge of the first clock, determines a first count of cycles of the reference clock between the first edge and the second edge, and communicates the first count to the second integrated circuit device. The second integrated circuit device receives the first count, provides a third edge of a second clock utilized by the second integrated circuit device, determines that a first number of cycles of the reference clock since providing the third edge is equal to the first count, and provides a fourth edge of the second clock in response to determining that the first number of cycles is equal to the first count.

A process includes a port of a bridge providing a reference clock signal to a first end of an interconnect extending between the first port and a network interface controller. The reference clock signal propagates over the interconnect to provide, at a second end of the interconnect, a delayed reference clock signal at the network interface controller. Pursuant to the process, the bridge senses a timing of the delayed reference clock signal. The process includes communicating management traffic between a network interface of a baseboard management controller and the network interface controller via the interconnect. The communication of the management traffic includes the port, responsive to the sensing of the timing of the delayed reference clock signal, synchronizing communication of data with the first end of the interconnect to the delayed reference clock signal.

A device includes feed-forward clock circuitry to provide a receiver (RX) clock to a sampler circuit that samples a data lane of a set of RX data lanes, the feed-forward clock circuitry having a temperature-induced delay. The device also includes an RX phase-locked loop (PLL) coupled between the feed-forward clock circuitry and the sampler circuit. The RX PLL includes a phase interpolator positioned in a feedback path of the RX PLL. The phase interpolator has a negative delay that matches the temperature-induced delay of the feed-forward clock circuitry to cause the sampler circuit to cancel out the common noise shared between the feed-forward clock circuitry and the data lane.

The various implementations described herein include methods and systems for synchronous audio playback. In one aspect, a method is performed at each of a plurality of electronic devices, each having an audio system, an internal clock, processors and memory storing programs for execution by the processors. Each device is configured for two-way communications with a server and associated with a user account. The device receives an identification of a first device as a common clock device that has a first internal clock being designated as a master clock. The device receives a synchronized audio playback command that includes audio data to be output and a future playback time. In response to receiving the audio data, the device determines a synchronized audio playback time. If the determined synchronized audio playback time has not yet occurred, the electronic device outputs the audio data based on the determined synchronized audio playback time.