A method for performing time-synchronization between a master clock of a master unit and a plurality of slave clocks of a corresponding plurality of slave units includes sending a forward time-synchronization message indicative of the master clock from the master unit to the plurality of slave units, in order to enable the plurality of slave units to time-synchronize their respective slave clocks with the master clock. The method also includes receiving a reverse time-synchronization message indicative of the respective slave clock from each of the plurality of slave units at a first validator. The method also includes time-synchronizing a plurality of validator clocks of the first validator to the corresponding plurality of slave clocks using the reverse time-synchronization messages from the plurality of slave units, and validating the time-synchronization between the plurality of slave clocks at the first validator based on the plurality of validator clocks.

In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.

A process includes a port of a bridge providing a reference clock signal to a first end of an interconnect extending between the first port and a network interface controller. The reference clock signal propagates over the interconnect to provide, at a second end of the interconnect, a delayed reference clock signal at the network interface controller. Pursuant to the process, the bridge senses a timing of the delayed reference clock signal. The process includes communicating management traffic between a network interface of a baseboard management controller and the network interface controller via the interconnect. The communication of the management traffic includes the port, responsive to the sensing of the timing of the delayed reference clock signal, synchronizing communication of data with the first end of the interconnect to the delayed reference clock signal.

A device includes feed-forward clock circuitry to provide a receiver (RX) clock to a sampler circuit that samples a data lane of a set of RX data lanes, the feed-forward clock circuitry having a temperature-induced delay. The device also includes an RX phase-locked loop (PLL) coupled between the feed-forward clock circuitry and the sampler circuit. The RX PLL includes a phase interpolator positioned in a feedback path of the RX PLL. The phase interpolator has a negative delay that matches the temperature-induced delay of the feed-forward clock circuitry to cause the sampler circuit to cancel out the common noise shared between the feed-forward clock circuitry and the data lane.

A transmission method includes generating one or more frames for content transfer using IP (Internet Protocol) packets, and transmitting the one or more generated frames by broadcast. Each of the one or more frames contains a plurality of second transfer units, each of the plurality of second transfer units contains one or more first transfer units, and each of the one or more first transfer units contains at least one of the IP packets. An object IP packet of the IP packets which is stored in a first transfer unit positioned at a head in the one or more frames contains reference clock information that indicates time for reproduction of the content in data structure different from data structure of an MMT (MPEG Media Transport) packet, and header compression processing on the object IP packet is omitted.

Techniques are disclosed relating to time synchronization in a network. In some embodiments, an apparatus includes a first circuit having a first clock configured to maintain a local time value for a node coupled to a network. The first circuit is configured to send a first message to a second circuit. The first message includes a first nonce. The second circuit has a second clock that maintains a reference time value for the network. The first circuit receives a second message from the second circuit, the second message including a second nonce and is associated with a timestamp identifying the reference time value. The first circuit compares the first nonce to the second nonce to determine whether the timestamp is valid and, in response to determining that the timestamp is valid, uses the timestamp to synchronize the first clock with the second clock.

Provided herein are systems and methods for synchronizing clocks and determining a range distance between two clocks using one or more timing signals that are communicated between the clocks. The determination can be made to also account for movement between the clocks such as if the clocks are converging (i.e., the distance between them is decreasing over time) or diverging (i., the distance between the clocks is increasing over time.) The systems and methods can utilize timing signals transmitted between two clocks that are synchronizing with another using the precision time protocol. In order to account for the increasing or decreasing distance between the clocks, the systems and methods can utilize Doppler shift data taken between the clocks to apply a correction factor to the timing signals. The timing signals and correction factor can be utilized to also determine a range distance between the clocks.

Disclosed are an electronic device and a method for controlling same. The disclosed electronic device re-samples data received from a first external electronic device, on the basis of the difference in speed between the clock speed of the first external electronic device and the clock speed of the disclosed electronic device, and transmits the re-sampled data to a second external electronic device.

The invention belongs to the technical field of time synchronization of computer co-simulation, and particularly relates to a time consistency synchronization method for distributed simulation. According to the time consistency synchronization method, a most appropriate master clock is selected according to votes, and then the other clocks in a network are controlled to synchronize by using the master clock, so that the consistency of data of each node and a time-related event in time logic is ensured. Even if a certain simulation node goes down, influences on the other links of the whole system are relatively small, which can effectively perform decentration, ensure the time consistency to the greatest extent, and ensure the correctness and the scale of a whole distributed system.

A method for synchronizing a first time domain with a second time domain of a system on chip includes a detection of at least one periodic trigger event generated in the first time domain, the second time domain or in a third time domain; acquisitions, made at the instants of the at least one trigger event, of the current timestamp values representative of the instantaneous states of the time domain(s) other than the trigger time domain; a comparison, made in the third time domain, between differential durations between current timestamp values which are respectively acquired successively; and a synchronization of the second time domain with the first time domain, on the basis of the comparison.