H04L7/0012

DATA HANDOFF BETWEEN TWO CLOCK DOMAINS SHARING A FUNDAMENTAL BEAT
20210157355 · 2021-05-27 ·

A data handoff controller includes a counter coupled to supply a count value indicative of a skew between a first clock signal and a second clock signal. The first and second clock signal have a fundamental beat frequency. A greatest common factor circuit is used to determine the fundamental beat frequency and the second is reset based on the beat frequency. A sampling circuit samples first clock domain data with the second clock signal. The sampling circuit is controlled to sample, at least in part, based on the count value. The count value can be used to impose a blackout window in which data is not sampled to avoid sampling data around data transitions of the first clock domain data. The count value can also be used to select an edge of the second clock signal to use for sampling the first clock domain data to ensure first clock domain data is not sampled during data transitions.

DECISION FEEDBACK EQUALIZATION CORRECTION OF EYE SCOPE MEASUREMENTS
20210126725 · 2021-04-29 ·

Methods and systems are described for obtaining a plurality of BER-specific correction values by comparing a first set of BER values obtained by sampling, at a sampling instant near the center of a signaling interval, a non-DFE corrected received signal with a second set of BER values obtained by sampling a DFE-corrected received signal at the sampling instant. A set of eye-scope BER measurements are obtained, each eye-scope BER measurement having a sampling offset relative to the sampling instant, a voltage offset value representing a voltage offset applied to alter a decision threshold, and an eye-scope BER value. A set of DFE-adjusted eye-scope BER measurements are generated by using BER-specific correction values to adjust the voltage offset values of the eye-scope BER measurements.

DIRECT CONVERSION RECEIVER USING COHERENT INTEGRATION
20210105036 · 2021-04-08 · ·

A receiver includes a circuit designed to process, based on a plurality of timed waveform reference locations, a waveform signal, the waveform signal comprising a message. The circuit may include a clock source, an input configured to receive the waveform signal, a time location reference circuit coupled to the clock source, the time location reference circuit designed to output the plurality of timed waveform reference locations, each timed waveform reference location being set by the clock, and a signal processing circuit coupled to the time location reference circuit, the signal processing circuit designed to generate an output voltage in a response to the waveform signal being inputted into the signal processing circuit through the input and processed at each timed waveform reference location from the series of timed waveform reference locations. A transmitter that generates the waveform signal can be also provided where the clocks are matched.

Device and method for correcting at least one transmission parameter

A method corrects at least one transmission parameter for data transmission between a sensor unit and a control unit. A sensor timing signal is generated by a sensor oscillator with a predetermined period. The at least one transmission parameter is determined on the basis of the sensor timing signal. A reference timing signal is generated by a reference oscillator with a predefined reference period. The sensor timing signal is compared with the reference timing signal. A deviation of a current period of the sensor timing signal from a reference period is determined on the basis of the comparison. The at least one transmission parameter is corrected on the basis of the determined deviation.

DATA SYNCHRONIZATION METHOD, DEVICE, EQUIPMENT, SYSTEM AND STORAGE MEDIUM

A data synchronization method, device, equipment, system and storage medium. Including: if a first data packet received by a slave device from a master device during a current Bluetooth low energy (BLE) connection interval is a new data packet, the slave device generates a hardware synchronization signal, which is a synchronization signal generated by a pure hardware circuit; if a data synchronization time of the slave device with the master device is a preset time in the current BLE connection interval, then the slave device performs data synchronization with the master device at the data synchronization time through triggering by the hardware synchronization signal.

Methods and apparatus for data synchronization in systems having multiple clock and reset domains

A data synchronization unit including first flip-flops, operating on a first clock domain and a reset of a second clock domain, sampling data from the first clock domain; a second flip-flop, operating in the first clock domain, sampling a request signal when enabled by a request pulse; a request signal path configured to delay the request signal by a first delay and to generate an enable signal for recirculation multiplexers in accordance with the delayed request signal; a reset signal synchronization path configured to delay the reset signal of the first clock domain by a second delay, wherein the second delay is shorter than the first delay; and multiplexers having first inputs for receiving outputs of the recirculation multiplexers, a second input for receiving a reset value of a programmable register, the multiplexers being configured to selectively output signals at inputs to outputs.

Estimating clock phase error based on channel conditions

Managing clock-data recovery for a modulated signal from a communication channel comprises: receiving the modulated signal and providing one or more analog signals, providing one or more digital input streams from samples of the analog signals, and processing the digital input streams to provide decoded digital data. The processing comprises: determining the decoded digital data based on information modulated over a plurality of frequency elements associated with the modulated signal, based at least in part on transforms of the digital input streams; a clock signal based on clock recovery from the digital input streams; and determining a clock phase error estimate associated with the determined clock signal based at least in part on a sum that includes different weights multiplied by different respective summands corresponding to different sets of frequency elements.

METHOD FOR MEASURING AND CORRECTING MULTIWIRE SKEW
20210075586 · 2021-03-11 ·

Methods and systems are described for sequentially obtaining a plurality of data streams, the plurality of data streams comprising a data stream in a current condition, a data stream in a skewed-forward condition, and a data stream in a skewed-backward condition, calculating, for each data stream in the plurality of data streams, a corresponding set of cost-function values by obtaining a corresponding set of eye measurements, the eye measurements obtained by adjusting a sampling threshold of a sampler generating a plurality of samples of the data stream, the plurality of samples comprising edge samples and data samples, wherein the data stream is sampled at a rate equal to twice a rate of the data stream and calculating the corresponding set of cost-function values based on the corresponding set of eye measurements, and generating a skew control signal based on a comparison of the sets of calculated cost-function values.

Multi-output synchronization

Systems and methods of generating a synchronized media content presentation using a plurality of media output systems communicably coupled to a respective plurality of network connected platforms are provided. A first network connected platform receives an IEEE 802.1AS master timing signal generated by Grand Master timing circuitry disposed in a second network connected platform. IEEE 802.1AS application service circuitry disposed in the first network connected platform determines an offset between a local timing signal and the receive master timing signal. Talker circuitry disposed in the first network connected platform synchronizes a media content presentation to the master timing signal and communicates a media/master timing signal synchronization signal to each of the network connected platforms. The media/master timing signal synchronization signal includes data representative of a media start location and a media start time referenced to the master timing signal.

OFDMA baseband clock synchronization

A method for synchronizing baseband clocks in an OFDMA wireless microphone system is disclosed. An example method includes receiving a plurality of pilot subcarriers from an audio transmitter. The method also includes determining a timing offset estimate based on the pilot subcarriers. The method further includes determining a tuning value by passing the timing offset estimate through a proportional-integral controller. The method still further includes determining a modified reference signal by modifying a reference oscillator based on the tuning value. And the method yet further includes controlling (i) an audio sample clock and (ii) an antenna data clock based on the modified reference signal.