A method at a first device for synchronising a first clock of the first device to a second clock of a second device, includes receiving a first message comprising an identifier from a third device; generating a first timestamp in dependence on the time at which the first message is received at the first device according to the first clock; receiving a second message from the second device comprising the identifier and a second timestamp, the second timestamp having been generated in dependence on the time at which the second device received the first message from the third device according to the second clock; and adjusting the first clock in dependence on a time difference between a time indicated by the first timestamp and a time indicated by the second timestamp.

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

A receiver includes a circuit designed to process, based on a plurality of timed waveform reference locations, a waveform signal, the waveform signal comprising a message. The circuit may include a clock source, an input configured to receive the waveform signal, a time location reference circuit coupled to the clock source, the time location reference circuit designed to output the plurality of timed waveform reference locations, each timed waveform reference location being set by the clock, and a signal processing circuit coupled to the time location reference circuit, the signal processing circuit designed to generate an output voltage in a response to the waveform signal being inputted into the signal processing circuit through the input and processed at each timed waveform reference location from the series of timed waveform reference locations. A transmitter that generates the waveform signal can be also provided where the clocks are matched.

A method for synchronizing a first time domain with a second time domain of a system on chip includes a detection of at least one periodic trigger event generated in the first time domain, the second time domain or in a third time domain; acquisitions, made at the instants of the at least one trigger event, of the current timestamp values representative of the instantaneous states of the time domain(s) other than the trigger time domain; a comparison, made in the third time domain, between differential durations between current timestamp values which are respectively acquired successively; and a synchronization of the second time domain with the first time domain, on the basis of the comparison.

A re-timer device includes transceiver circuitry. The transceiver circuitry includes clock generation circuitry and first receiver circuitry. The clock generation circuitry generates a first clock signal. The first receiver circuitry receives the first clock signal and a first input signal. The first receiver circuitry generates a first frequency offset value based on the first input signal and the first clock signal. The first input signal has a first frequency and the first clock signal has a second frequency different than the first frequency. The first receiver circuitry outputs the first frequency offset value.

A system and method involve using sferic signals to synchronize clocks and/or determine relative receiver positions within a communications network. A sferic signal is detected, encoded, and then identified. A time-difference-of-arrival (TDOA) for the sferic signal is then calculated. A clock error estimate is determined from the TDOA. The clock error estimate is then used to synchronize clocks and/or determine relative receiver positions.

A system, in some embodiments, comprises: an antenna; a receiver, coupled to the antenna, to receive wireless signals from another electronic device; a signal processor (SP) coupled to the receiver; and a phase locked loop (PLL), distributed among the receiver and the SP, to synchronize the frequency of a data sampling clock used by the SP with the frequency of a source clock determined by the receiver.

A system includes a link having one or more lanes associated with transmitting data and one or more lanes associated with transmitting a clock signal. The system includes a device coupled with the link, the device to receive a signal via the one or more lanes associated with transmitting the clock signal and determine a number of pulses associated with the signal over a period. The device is further to determine the number of pulses associated with the signal fail to satisfy a predetermined condition relating to a specified number of pulses for the period and initiate a power-down sequence in response to determining the number of pulses that fail to satisfy the predetermined condition relating to the specified number of pulses for the period.

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

A method of measuring linearity characteristics of a delay line may be provided. The method may include generating an output signal from a receiver including a delay line. The method may also include measuring linearity characteristics of the delay line based on a target performance parameter of the output signal.