A method for synchronizing time in an Ethernet-based network having a master network subscriber and a slave network subscriber includes sending out a first telegram via the master network subscriber, where the slave subscriber receives the first telegram at a first receipt time value of a local system time and stores the first receipt time value. The method can also include reading out the first receipt time value via the master subscriber, sending out a second telegram by the master subscriber, where the slave subscriber receives the second telegram at a second receipt time value of the local system time and stores the second receipt time value, and reading out the second receipt time value via the master network subscriber. A speed parameter of the local system time can be calculated from the receipt time values via the master network subscriber, and transmitted to the slave subscriber.

A analog equalizer includes: an adjusting circuit, generating an adjustment signal and a selection signal; a cascaded equalization circuit, receiving the adjustment signal, and adjusting at least one of a tunable resistor, a tunable capacitor and a tunable current source in the multi-stage equalization circuit according to the adjustment signal to perform an equalization process on a signal to be equalized; and an analog multiplexer, coupled to the cascaded equalization circuit and the adjusting circuit, selecting and outputting an equalized signal outputted from one stage of the multi-stage equalization circuit according to the selection signal. Wherein, the adjusting circuit adjusts the adjustment signal and the selection signal according to the equalized signal outputted from the analog multiplexer and a target equalization value.

A method for indicating one-way latency in a data network, with continuous clock synchronization, between first and second node having clocks that are not synchronized with each other includes a continuous synchronization session and a measurement session. The method repetitively sends predetermined synchronization messages from the first node to the second node and from the second node to the first node, calculates a round trip time for each message at the first node, updates a synchronization point if the calculated round trip time is smaller than a previously calculated round trip time, stores the updated synchronization points of a synchronization window, and calculates a virtual clock from the updated synchronization points of the synchronization window. The measurement session collects multiple measurements of one-way latency between the first and second nodes using the virtual clock, and generates a latency profile by interpolating the multiple measurements.

The present application discloses an asynchronous sampling architecture and a chip. The asynchronous sampling architecture is configured to receive a first input data string from the peer end, and the asynchronous sampling architecture includes: a first register, configured to buffer a first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end; and a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out as a first output data string from the first register according to the gated clock.

A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the frequency offset, or rate of change of the frequency offset, between an arriving signal and the recovered clock signal.

A repeater (1) particularly suitable for a time-division duplex transmission of communication signals is provided. The repeater (1) comprises a master unit (2) for communicating with a base station (3) of a wireless network, at least one remote unit (4) for communicating with a network terminal, as well as a waveguide (11) connecting the remote unit (4) with the master unit (2) for transmitting the communication signals in an uplink direction (6) from the remote unit (4) to the master unit (2) and in a downlink direction (5) from the master unit (2) to the remote unit (4). Both the master unit (2) and the remote unit (4) comprise one switch (19, 20) each for changing over the signal transmission between uplink direction (6) and downlink direction (5). Both switches (19, 20) are selected by a synchronizing unit (21) arranged in the master unit (2), the synchronizing unit (21) being designed for determining a clock pulsing from the communication signal fed to the master unit (2)—in particular from the base station (3)—and for supplying a control signal corresponding to this clock pulsing to the switches (19, 20).

A video processing system can include a buffer, a packetizer block that is coupled to the buffer, and a buffer controller that is coupled to the buffer and the packetizer block. The buffer is capable of receiving and storing a video signal as video data. The packetizer block is capable of packetizing video data read from the buffer and sending packetized data to a node external to the video processing system. The buffer controller is capable of controlling an amount of video data included within each packet generated by the packetizer block.

A dynamic data distribution method in a private network and an associated electronic device are provided. The private network includes: a first pairing connection between a first electronic device, a second electronic device, and a second pairing connection between the first electronic device and a third electronic device. The method includes the steps of: receiving sensor data from the second electronic device by the first electronic device; notifying the second electronic device to build a third pairing connection with the third electronic device according to a determination result between the first electronic device and the third electronic device; and terminating the first pairing connection and retrieving the sensor data from the second electronic device through the third electronic device by the first electronic device when the third pairing connection has been built.

A data reading circuit including a phase difference determining module, a time delay detection module, and a reading control module, and the phase difference determining module is connected to the echo clock signal and a clock signal of the second clock domain. The phase difference determining module is configured to determine a phase difference between the echo clock signal and the clock signal of the second clock domain; the time delay detection module is configured to detect a time delay value in transmission of data from a buffer to a flip-flop; and the reading control module is configured to determine, according to the phase difference and the time delay value, a triggering edge, at which the flip-flop can read data output by the buffer, of the clock signal of the second clock domain.

A system for monitoring a machine includes first and second mobile units. The first mobile unit includes an emitter, a clock in communication with the emitter, and a sensor in communication with the clock. The second mobile unit includes a detector, a clock in communication with the detector, and a sensor in communication with the clock. The detector of the second mobile unit is configured to detect a signal from the emitter of the first mobile unit, and the clocks in the first and second mobile units are configured to be synchronized in response to the detection of the signal.