A time synchronization system includes a master and slave devices connected to each other via a data bus and a signal line dedicated to transmission of a fixed-period signal. The master device transmits the fixed-period signal through the signal line regularly at a transmission period, and transmits start time information indicating a transmission start time at which transmission of the fixed-period signal is started and transmission period information indicating the transmission period for the fixed-period signal through the data bus. The slave device counts a number of times the fixed-period signal is received and calculates, as a current time in the master device, a transmission time at which the master device transmits the fixed-period signal based on the number of times the fixed-period signal is received. The slave device corrects the time to the calculated current time in the master device.

A method for synchronizing a first time domain with a second time domain of a system on chip includes a detection of at least one periodic trigger event generated in the first time domain, the second time domain or in a third time domain; acquisitions, made at the instants of the at least one trigger event, of the current timestamp values representative of the instantaneous states of the time domain(s) other than the trigger time domain; a comparison, made in the third time domain, between differential durations between current timestamp values which are respectively acquired successively; and a synchronization of the second time domain with the first time domain, on the basis of the comparison.

The various implementations described herein include methods and systems for synchronous audio playback. In one aspect, a method is performed at each of a plurality of electronic devices, each having an audio system, an internal clock, processors and memory storing programs for execution by the processors. Each device is configured for two-way communications with a server and associated with a user account. The device receives an identification of a first device as a common clock device that has a first internal clock being designated as a master clock. The device receives a synchronized audio playback command that includes audio data to be output and a future playback time. In response to receiving the audio data, the device determines a synchronized audio playback time. If the determined synchronized audio playback time has not yet occurred, the electronic device outputs the audio data based on the determined synchronized audio playback time.

A clock synchronization packet exchanging method includes sending, by a first device in a Flexible Ethernet (FlexE) group, a first FlexE instance at a first physical layer (PHY), where the first FlexE instance includes a clock synchronization packet, and a second FlexE instance sent by the first device in the FlexE group at a second PHY also includes a clock synchronization packet. The clock synchronization packets are carried in a plurality of FlexE instances transmitted between a transmit end and a receive end in the FlexE group.

In a hybrid network comprising both guided and wireless communications technologies, a grandmaster clock is designated in one portion of the network and can be propagated across to the other portion by means of a timing synchronization message. This message may include timestamping information and other information to enable recipient devices to correctly synchronize to the grandmaster clock.

A method minimizes audio and video streaming delays between a video source and a video sink. A receiver receives a netsync message from a transmitter that communicates with the video source to receive input video. The netsync message is generated by the transmitter in accordance with the input video and indicates a display pointer of the transmitter. In accordance with the netsync message, the receiver adaptively outputs a set of timing control signals that is transmitted to the video sink, thereby minimizing the latency between the vertical synchronization (VSYNC) of the transmitter and the VSYNC of the receiver.

In one embodiment, a network device, includes a network interface port configured to receive data symbols from a network node over a packet data network, at least some of the symbols being included in data packets, and controller circuitry including physical layer (PHY) circuitry, which includes receive PHY pipeline circuitry configured to process the received data symbols, and a counter configured to maintain a counter value indicative of a number of the data symbols in the receive PHY pipeline circuitry.

A baud-rate phase detector uses two error samplers. One error sampler is used to determine whether the sampling time is too early error detection. The other is used to determine whether sampling time is too late. The early error sampler is configured to use a first threshold voltage. The late error sampler is configured to use a second threshold voltage. By adjusting the voltage difference between the first threshold voltage and the second threshold voltage, the phase difference between the local timing reference clock and the transitions of the data signal may be adjusted. The phase difference between the local timing reference clock and the transitions of the data signal may be adjusted to improve or optimize a desired receiver characteristic such as bit error rate or signal eye opening.

A transmission method includes generating one or more frames for content transfer using IP (Internet Protocol) packets, and transmitting the one or more generated frames by broadcast. Each of the one or more frames contains a plurality of second transfer units, each of the plurality of second transfer units contains one or more first transfer units, and each of the one or more first transfer units contains at least one of the IP packets. An object IP packet of the IP packets which is stored in a first transfer unit positioned at a head in the one or more frames contains reference clock information that indicates time for reproduction of the content in data structure different from data structure of an MMT (MPEG Media Transport) packet, and header compression processing on the object IP packet is omitted.

The invention belongs to the technical field of time synchronization of computer co- simulation, and particularly relates to a time consistency synchronization method for distributed simulation. According to the time consistency synchronization method, a most appropriate master clock is selected according to votes, and then the other clocks in a network are controlled to synchronize by using the master clock, so that the consistency of data of each node and a time-related event in time logic is ensured. Even if a certain simulation node goes down, influences on the other links of the whole system are relatively small, which can effectively perform decentration, ensure the time consistency to the greatest extent, and ensure the correctness and the scale of a whole distributed system.