A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.

One or more examples relate, generally to phase and frequency error processing. An apparatus includes a phase path and a frequency path. The phase path processes phase error of communications between network nodes. The phase path includes a closed-loop feedback loop controller. The frequency path processes frequency error of the communications between the network nodes. The frequency path is separate from the phase path. A method of processing phase error and frequency error includes selecting first packets for phase processing, processing the first packets for phase error, selecting second packets for frequency processing, and processing the second packets for frequency error independently of the processing of the first packets.

A communication system includes: a plurality of sensor terminals each including a clock indicating an individual time and configured to detect sensing information related to a user and information detection time at which the sensing information has been detected; a management terminal configured to retain a reference time and adapted to communicate with the plurality of sensor terminals; and a relationship analysis unit configured to analyze a relationship among the users of the plurality of sensor terminals, in which the management terminal acquires the sensing information and the information detection time from each of the plurality of sensor terminals and corrects the information detection time acquired from each of the plurality of sensor terminals based on a lag between the individual time acquired from the corresponding sensor terminal and the reference time, and the relationship analysis unit analyzes the relationship using the sensing information and the corrected information detection time.

A system, method and computer program determine estimated sensor data using time-series projection. The system comprises processing circuitry configured to obtain a plurality of samples of sensor data of the sensor. The processing circuitry is configured to obtain information on a time offset between the sensor data of the sensor and a reference time. The processing circuitry is configured to perform a time-series projection based on the plurality of samples of the sensor data. The time-series projection is performed using an auto-regressive statistical model. The processing circuitry is configured to determine an estimate of the sensor data for the reference time based on the time-series projection and based on the time offset between the sensor data and the reference time. Thus, the time-series projection may be used to bridge the time offset between the sensor data of the sensor and the reference time.

A wireless audio system including a transmitter using multiple antenna diversity techniques for different signal types is provided. Multipath performance may be optimized, along with improved spectral efficiency of the system.

A method of synchronizing time across a plurality of time domains between a master node and a slave node is provided. The method comprises transmitting, by the master node, a reference time indicated by a hardware clock of the master node to the slave node, synchronizing, by the slave node, a hardware clock of the slave node to the reference time indicated by the hardware clock of the master node, transmitting, by an offset clock layer of the master node, an offset of a first time domain among the plurality of time domains to an offset clock layer of the slave node, and obtaining, by the PTP layer of the slave node, a time in the first time domain by applying the offset of the first time domain to a reference time indicated by the hardware clock of the slave node.

A slave node calculates and stores a propagation delay generated when exchanging a message with a master node. The master node transmits a reference time indicated by a hardware clock of the master node, and the slave node synchronizes a hardware clock of the slave node to the reference time indicated by the hardware clock of the master node. The master node transmits a time value in a first time domain to the slave node, where the time value is calculated by the master node by adding an offset of the first time domain to the reference time. The slave node calculates the offset using the time value and the stored propagation delay, and obtains a time in the first time domain by applying the calculated offset to a reference time indicated by the hardware clock of the slave node.

The present technology relates to a data processing apparatus and a data processing method that enable correct clock synchronization by use of clock information. The data processing apparatus receives a digital broadcast signal so as to process content included in the digital broadcast signal and clock information also included therein for use in presentation synchronization on the content and sends via a transmission path the processed content and clock information to another data processing apparatus that presents the received content. On the other hand, the another data processing apparatus receives via the transmission path the content and clock information sent from the data processing apparatus so as to process presentation synchronization on the received content on the basis of the received clock information. The present technology is applicable to data processing apparatuses configured to process content, for example.

A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

Embodiments include systems and methods for applying a controllable early/late offset to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). For example, slope asymmetry around the first precursor of the channel pulse response for the SERDES can tend to skew at-rate CDR determinations of whether to advance or retard clocking. Accordingly, embodiments use asymmetric voting thresholds for generating each of the advance and retard signals in an attempt to de-skew the voting results and effectively tune the CDR to a position either earlier or later than the first precursor zero crossing (i.e., h(−1)=0) position. This can improve link margin and data recovery, particularly for long data channels and/or at higher data rates.