A network device adapted for sending a synchronization packet to a slave device. The synchronization packet includes a timestamp field and a correction field. The network device includes a counting circuit, a communication chip, and a processor. The counting circuit is configured to provide a calendar time TOD. The communication chip includes a first port, a second port, and a timestamp circuit which has a bit number N. The processor is coupled to the first port of the communication chip. The processor is configured to: obtain a remainder R according to the calendar time TOD and the bit number N; and write the calendar time TOD and the remainder R into the synchronization packet.

An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.

A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

A network device may be operable to manage a network connection of customer premise equipment (CPE). While the CPE is operating in a normal mode of operation, the network device may communicate with the CPE utilizing one or more messages of a first type. While the CPE is operating in a low-power mode of operation, the network device may communicate with the CPE utilizing one or more messages of a second type. The network device may be operable to determine a particular program identifier to be utilized for messages the first type of message, and transmit such message(s) to the CPE. The message(s) transmitted while the CPE is in a low-power mode may comprise MPEG-TS packets having the particular program identifier. The message(s) transmitted while the CPE is not in the low-power mode may comprises MPEG-TS packets not having the particular program identifier.

Implementations of the present disclosure involve an apparatus and/or method for adjusting a counter in a computing system to account for drift of the counter value over time compared to another counter of the system. In particular, a processor of the computing system that includes a local counter component may access a counter component of another processor of the system, referred to as the reference counter. By comparing the value of the reference counter to the local counter, the processor may determine any drift that may have occurred over a period of time in the local counter. The calculated drift, or counter error, may be converted into one or more adjustments to the local counter to synchronize the local counter with the reference counter. In one embodiment, the adjustment to the local counter includes increasing the rate at which the local counter is incremented for a period of time.

A repeater (1) particularly suitable for a time-division duplex transmission of communication signals is provided. The repeater (1) comprises a master unit (2) for communicating with a base station (3) of a wireless network, at least one remote unit (4) for communicating with a network terminal, as well as a waveguide (11) connecting the remote unit (4) with the master unit (2) for transmitting the communication signals in an uplink direction (6) from the remote unit (4) to the master unit (2) and in a downlink direction (5) from the master unit (2) to the remote unit (4). Both the master unit (2) and the remote unit (4) comprise one switch (19, 20) each for changing over the signal transmission between uplink direction (6) and downlink direction (5). Both switches (19, 20) are selected by a synchronizing unit (21) arranged in the master unit (2), the synchronizing unit (21) being designed for determining a clock pulsing from the communication signal fed to the master unit (2)—in particular from the base station (3)—and for supplying a control signal corresponding to this clock pulsing to the switches (19, 20).

Embodiments of this disclosure provide an apparatus and method for estimating a frequency offset, an apparatus and method for estimating a channel spacing and a system. The apparatus for estimating a frequency offset includes: a synchronization extracting unit configured to perform a training sequence synchronization extraction on a receiving sequence containing a periodic training sequence to obtain the training sequence; a delay correlation processing unit configured to parallelly perform autocorrelation operations of different delay amounts on the training sequence to obtain multiple parallel correlation sequences; a superimposition processing unit configured to perform a superimposition operation on the multiple parallel correlation sequences to obtain a single sequence; and a frequency offset estimating unit configured to determine a frequency offset according to a phase of a synchronization position of the single sequence in the training sequence. With the embodiments of this disclosure, anti-noise characteristic of the frequency offset estimation may be improved.

A method for synchronisation of an emitter of FBMC system with a RACH channel. On the emitter, a pseudo-random sequence with an initial offset in relation to a reference sequence is inserted into the spectral band of the RACH channel. On the receiver, the sequence received on the RACH channel is estimated using a sliding FFT using a starting point and correlated with the reference sequence. The position of the starting point leading to the highest correlation peak is selected as well as the correlation position corresponding to this peak, with these two positions making it possible to determine the offset of the sequence received with the reference sequence. This offset is transmitted to the emitter and the latter deduces from it a delay to be compensated in the emission in order to synchronise with the receiver.

The present technology relates to a data processing apparatus and a data processing method that enable correct clock synchronization by use of clock information. The data processing apparatus receives a digital broadcast signal so as to process content included in the digital broadcast signal and clock information also included therein for use in presentation synchronization on the content and sends via a transmission path the processed content and clock information to another data processing apparatus that presents the received content. On the other hand, the another data processing apparatus receives via the transmission path the content and clock information sent from the data processing apparatus so as to process presentation synchronization on the received content on the basis of the received clock information. The present technology is applicable to data processing apparatuses configured to process content, for example.

A communication apparatus is one of a plurality of communication apparatuses included in a communication system where a first communication apparatus transmits data via a transmission path in synchronization with communication by a second communication apparatus. The communication apparatus includes a switching element setting a signal level on the transmission path to a dominant level by being turned on; a driving circuit driving the switching element. and a control circuit giving an on command that instructs the driving circuit to turn the switching element on in response to an edge at which a signal level on the transmission path changes from a recessive level to a dominant level being detected. The driving circuit or the control circuit is further configured to shorten a delay time from when the edge is detected to when the switching element is turned on.