A reception apparatus includes a detection unit that detects occurrence of a phase slip in phase estimation values of time-series received symbol data, and determines an inclination of the phase slip, a delay processing unit that generates first received signal data obtained by delaying received signal data obtained from the time-series received symbol data by one symbol time interval, a phase shift unit that generates second received signal data by performing phase shift according to the inclination, only in a period in which one symbol time interval elapses, on only the received signal data of a symbol time at which the occurrence of the phase slip is detected among pieces of the received signal data, and a remainder processing unit that derives a remainder of a difference between the second received signal data and the first received signal data.

A transmitter circuit includes a phase locked loop circuit, having one or more operational characteristics indicative of an operating state of the phase locked loop circuit. The phase locked loop circuit is configured to generate a frequency signal. The transmitter circuit also includes a power amplifier configured to selectively drive an antenna with a drive signal according to the frequency signal, and a programmable delay circuit configured to controllably extend a propagation delay between the frequency signal and the drive signal of the power amplifier. The programmable delay circuit is programmed such that a first value of a particular operational characteristic of the phase locked loop circuit is substantially equal to a second value of the operational characteristic of the phase locked loop circuit. The first value is measured with the power amplifier not driving the antenna. The second value is measured with the power amplifier driving the antenna.

In one embodiment, a network device, includes a network interface port configured to receive data symbols from a network node over a packet data network, at least some of the symbols being included in data packets, and controller circuitry including physical layer (PHY) circuitry, which includes receive PHY pipeline circuitry configured to process the received data symbols, and a counter configured to maintain a counter value indicative of a number of the data symbols in the receive PHY pipeline circuitry.

The present disclosure is directed to timestamp detection using a cable modem and to a control apparatus, control device and control method for detecting time stamps in various signals such as orthogonal frequency division multiplexing (OFDM) signals. The control apparatus comprising processing circuitry being configured to obtain information a channel frequency response of the multi-path channel, the channel frequency response being based on a signal comprising a sequence of symbols. The processing circuitry is configured to transform the channel frequency response into a channel impulse response. The processing circuitry is configured to identify a peak in the channel impulse response. The processing circuitry is configured to determine a timestamp offset time between the peak in the channel impulse response and a trigger time indicative of a beginning of a symbol in the signal. The processing circuitry is configured to synchronize the device clock based on the timestamp offset time.

Disclosed is a method of operating a network, the network having one or more nodes which are in communication with a server, the server including or being in communication with a high precision time source, to estimate a time delay between the server and each node, comprising initiating a delay request from the server which is transported over a transport layer to the node, the server receiving a delay response from the node receiving the delay request, wherein a timestamp for the delay request and a timestamp for the delay response are times recorded from the high precision time source, wherein the time delay is estimated from half of a time difference between the timestamps.

A system and method for one-way ranging is disclosed. The system comprises a transmitter, also referred to as a tag, transmitting a packet having a sounding sequence. The receiver, also referred to as the locator, receives the sounding sequence. The receiver measures and saves the phase at a plurality of points in time. The sounding sequence has two frequencies, which are additive inverses of one another. A discrete Fourier transform is performed on the plurality of phase measurements to determine the phase of each of the two frequencies. The difference between these two frequencies is related to the time that the packet traveled. Additionally, a calibration of the transmit path and/or receive path may be performed to improve the accuracy of the results.

A method for synchronizing baseband clocks in an OFDMA wireless microphone system is disclosed. An example method includes receiving a plurality of pilot subcarriers from an audio transmitter. The method also includes determining a timing offset estimate based on the pilot subcarriers. The method further includes determining a tuning value by passing the timing offset estimate through a proportional-integral controller. The method still further includes determining a modified reference signal by modifying a reference oscillator based on the tuning value. And the method yet further includes controlling (i) an audio sample clock and (ii) an antenna data clock based on the modified reference signal.

A physical layer (PHY) processor of a network device receives a timing message via an external network and generates a first timestamp using a first local-domain clock used by the PHY processor. The PHY processor transfers the timing message and the first timestamp to a packet processor of the network device via an internal communication link. The packet processor generates a second timestamp for the timing message using a domain-specific clock. The packet processor determines a delay value using the first timestamp, the delay value accounting for a time delay corresponding to the transfer of the timing message within the network device from the PHY processor to the packet processor. The packet processor adjusts the second timestamp using the delay value to generate an adjusted domain-specific timestamp for the timing message.

A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

In the related art, since there is a difference in communication delay time in a round-trip communication path due to packet clogging in a network configuration using a network relay device, there is a problem that time cannot be synchronized. In order to solve the above problem, in the present invention, a time synchronization unit 131 is controlled by the time synchronization control unit 130 to perform time synchronization once, delays of an egress path and an ingress path of the time packet on the basis of the synchronization time are calculated, and time synchronization processing is executed using a time of the time packet in a case where the calculated values are equal to each other.